Ðþí  7    8  34   (            Ì  2ü                                                         xlnx,zynq-zc706 xlnx,zynq-7000           &Xilinx ZC706 board     cpus                                 cpu@0            arm,cortex-a9            ,cpu          8             <               C  è         Q            ] 
,+ B@  B@         n         cpu@1            arm,cortex-a9            ,cpu          8            <               n            fpga-full            fpga-region          v                                            pmu@f8891000             arm,cortex-a9-pmu            †                             ‘            8ø‰    ø‰0          fixedregulator           regulator-fixed          ¢VCCPINT          ± B@         É B@          á          ó         n         replicator            arm,coresight-static-replicator          <            .      /        apb_pclk dbg_trc dbg_apb       out-ports                                port@0           8       endpoint                        n            port@1           8      endpoint                        n               in-ports       port       endpoint                        n                  axi          simple-bus                                    ‘                adc@f8007100             xlnx,zynq-xadc-1.00.a            8ø q              †                   ‘            <            can@e0008000             xlnx,zynq-can-1.0         	  #disabled             <            $        can_clk pclk             8à €             †                   ‘           *   @        8   @      can@e0009000             xlnx,zynq-can-1.0         	  #disabled             <            %        can_clk pclk             8à              †       3            ‘           *   @        8   @      gpio@e000a000            xlnx,zynq-gpio-1.0          F            <      *         R         b        w            ‘            †                   8à              ˆdefault         –         i2c@e0004000             cdns,i2c-r1p10          #okay             <      &         ‘            †                   8à @                                        €        ˆdefault         –   	   i2c-mux@74           nxp,pca9548                                    8   t   i2c@0                                      8       clock-generator@5d          °             silabs,si570            ½   2         8   ]        Ó	P/         Ùî          i2c@1                                      8      hdmi-tx@39           adi,adv7511          8   9        à           ðyuv422          1x                     %evenly           i2c@2                                      8      eeprom@54            atmel,24c08          8   T         i2c@3                                      8      gpio@21          ti,tca6416           8   !         R        F            i2c@4                                      8      rtc@51           nxp,pcf8563          8   Q         i2c@7                                      8      ucd90120@65          ti,ucd90120          8   e               i2c@e0005000             cdns,i2c-r1p10        	  #disabled             <      '         ‘            †       0            8à P                                    interrupt-controller@f8f01000            arm,cortex-a9-gic           w            b         8øð    øð             n         cache-controller@f8f02000            arm,pl310-cache          8øð              †                  =                 N                  ^        l         memory-controller@f8006000           xlnx,zynq-ddrc-a05           8ø `          serial@e0000000          xlnx,xuartps cdns,uart-r1p8       	  #disabled             <            (        uart_clk pclk            8à               †                serial@e0001000          xlnx,xuartps cdns,uart-r1p8         #okay             <            )        uart_clk pclk            8à              †       2           ˆdefault         –   
      spi@e0006000             xlnx,zynq-spi-r1p6           8à `          	  #disabled             ‘            †                   <            "        ref_clk pclk                                    spi@e0007000             xlnx,zynq-spi-r1p6           8à p          	  #disabled             ‘            †       1            <            #        ref_clk pclk                                    ethernet@e000b000            cdns,zynq-gem cdns,gem           8à °            #okay             †                   <                          pclk hclk tx_clk                                    	  xrgmii-id                       ˆdefault         –      ethernet-phy@7           8            ,ethernet-phy             n            ethernet@e000c000            cdns,zynq-gem cdns,gem           8à À          	  #disabled             †       -            <                          pclk hclk tx_clk                                    memory-controller@e000e000        !   arm,pl353-smc-r2p1 arm,primecell             8à à          	  #disabled            memclk apb_pclk          <            ,      0           á             â             ä                                  nand-controller@0,0          arm,pl353-nand-r2p1          8                 	  #disabled                                       mmc@e0100000             arasan,sdhci-8.9a           #okay            clk_xin clk_ahb          <                      ‘            †                   8à             ˆdefault         –         mmc@e0101000             arasan,sdhci-8.9a         	  #disabled            clk_xin clk_ahb          <            !         ‘            †       /            8à          slcr@f8000000                                  !   xlnx,zynq-slcr syscon simple-mfd             8ø                         n      clkc@100            °            xlnx,ps7-clkc           Œ         j  ˜armpll ddrpll iopll cpu_6or4x cpu_3or2x cpu_2x cpu_1x ddr2x ddr3x dci lqspi smc pcap gem0 gem1 fclk0 fclk1 fclk2 fclk3 can0 can1 sdio0 sdio1 uart0 uart1 spi0 spi1 dma usb0_aper usb1_aper gem0_aper gem1_aper sdio0_aper sdio1_aper spi0_aper spi1_aper can0_aper can1_aper i2c0_aper i2c1_aper uart0_aper uart1_aper gpio_aper lqspi_aper smc_aper swdt dbg_trc dbg_apb            8              «ü U         n         rstc@200             xlnx,zynq-reset          8      H        ¼           É         pinctrl@700          xlnx,pinctrl-zynq            8              É      gem0-default             n      mux       
  Ðethernet0           Ùethernet0_0_grp       conf            Ùethernet0_0_grp         à            ê         conf-rx       $  öMIO22 MIO23 MIO24 MIO25 MIO26 MIO27          û               conf-tx       $  öMIO16 MIO17 MIO18 MIO19 MIO20 MIO21          !         2      mux-mdio            Ðmdio0           Ùmdio0_0_grp       conf-mdio           Ùmdio0_0_grp         à            ê            2         gpio0-default            n      mux         Ðgpio0         &  Ùgpio0_7_grp gpio0_46_grp gpio0_47_grp         conf          &  Ùgpio0_7_grp gpio0_46_grp gpio0_47_grp           à            ê         conf-pull-up            öMIO46 MIO47          ?      conf-pull-none          öMIO7             2         i2c0-default             n   	   mux         Ùi2c0_10_grp         Ði2c0          conf            Ùi2c0_10_grp          ?        à            ê            sdhci0-default           n      mux         Ùsdio0_2_grp         Ðsdio0         conf            Ùsdio0_2_grp         à            ê            2      mux-cd          Ùgpio0_14_grp          	  Ðsdio0_cd          conf-cd         Ùgpio0_14_grp             û         ?        à            ê         mux-wp          Ùgpio0_15_grp          	  Ðsdio0_wp          conf-wp         Ùgpio0_15_grp             û         ?        à            ê            uart1-default            n   
   mux         Ùuart1_10_grp            Ðuart1         conf            Ùuart1_10_grp            à            ê         conf-rx         öMIO49            û      conf-tx         öMIO48            2         usb0-default             n      mux         Ùusb0_0_grp          Ðusb0          conf            Ùusb0_0_grp          à            ê         conf-rx         öMIO29 MIO31 MIO36            û      conf-tx       6  öMIO28 MIO30 MIO32 MIO33 MIO34 MIO35 MIO37 MIO38 MIO39            2               dmac@f8003000            arm,pl330 arm,primecell          8ø 0             ‘         .  Labort dma0 dma1 dma2 dma3 dma4 dma5 dma6 dma7         l   †                                                         (          )          *          +           \            <            	  apb_pclk          devcfg@f8007000          xlnx,zynq-devcfg-1.0             8ø p             ‘            †                   <              ref_clk         É            n         timer@f8f00200           arm,cortex-a9-global-timer           8øð              †                 ‘            <            timer@f8001000           ‘         $   †       
                             	   cdns,ttc             <               8ø           timer@f8002000           ‘         $   †       %          &          '         	   cdns,ttc             <               8ø            timer@f8f00600           ‘            †                 arm,cortex-a9-twd-timer          8øð              <            usb@e0002000          "   xlnx,zynq-usb-2.20a chipidea,usb2           #okay             <               ‘            †                   8à              gulpi            phost            x           ˆdefault         –         usb@e0003000          "   xlnx,zynq-usb-2.20a chipidea,usb2         	  #disabled             <               ‘            †       ,            8à 0            gulpi          watchdog@f8005000            <      -         cdns,wdt-r1p2            ‘            †       	            8ø P            €   
      etb@f8801000          "   arm,coresight-etb10 arm,primecell            8ø€             <            .      /        apb_pclk dbg_trc dbg_apb       in-ports       port       endpoint                        n                  tpiu@f8803000         !   arm,coresight-tpiu arm,primecell             8ø€0             <            .      /        apb_pclk dbg_trc dbg_apb       in-ports       port       endpoint                        n                  funnel@f8804000       *   arm,coresight-static-funnel arm,primecell            8ø€@             <            .      /        apb_pclk dbg_trc dbg_apb       out-ports      port       endpoint                        n               in-ports                                 port@0           8       endpoint                        n            port@1           8      endpoint                        n            port@2           8      endpoint                   ptm@f889c000          "   arm,coresight-etm3x arm,primecell            8ø‰À             <            .      /        apb_pclk dbg_trc dbg_apb            Œ      out-ports      port       endpoint                        n                  ptm@f889d000          "   arm,coresight-etm3x arm,primecell            8ø‰Ð             <            .      /        apb_pclk dbg_trc dbg_apb            Œ      out-ports      port       endpoint                        n                     aliases         /axi/ethernet@e000b000          š/axi/i2c@e0004000           Ÿ/axi/serial@e0001000            §/axi/mmc@e0100000         memory@0             ,memory           8    @         chosen          ¬            µserial0:115200n8          phy0             usb-nop-xceiv           Á             n            	#address-cells #size-cells compatible model device_type reg clocks clock-latency cpu0-supply operating-points phandle fpga-mgr ranges interrupts interrupt-parent regulator-name regulator-min-microvolt regulator-max-microvolt regulator-boot-on regulator-always-on clock-names remote-endpoint status tx-fifo-depth rx-fifo-depth #gpio-cells gpio-controller interrupt-controller #interrupt-cells pinctrl-names pinctrl-0 clock-frequency #clock-cells temperature-stability factory-fout adi,input-depth adi,input-colorspace adi,input-clock adi,input-style adi,input-justification arm,data-latency arm,tag-latency cache-unified cache-level phy-mode phy-handle fclk-enable clock-output-names ps-clk-frequency #reset-cells syscon function groups slew-rate io-standard pins bias-high-impedance low-power-disable low-power-enable bias-disable bias-pull-up interrupt-names #dma-cells phy_type dr_mode usb-phy timeout-sec cpu ethernet0 i2c0 serial0 mmc0 bootargs stdout-path #phy-cells 