Ðþí  )Œ   8  &ø   (            ”  &À                                                      #   adapteva,parallella xlnx,zynq-7000           &Adapteva Parallella board      cpus                                 cpu@0            arm,cortex-a9            ,cpu          8             <               C  è         Q            ] 
,+ B@  B@         n         cpu@1            arm,cortex-a9            ,cpu          8            <               n            fpga-full            fpga-region          v                                            pmu@f8891000             arm,cortex-a9-pmu            †                             ‘            8ø‰    ø‰0          fixedregulator           regulator-fixed          ¢VCCPINT          ± B@         É B@          á          ó         n         replicator            arm,coresight-static-replicator          <            .      /        apb_pclk dbg_trc dbg_apb       out-ports                                port@0           8       endpoint                        n            port@1           8      endpoint                        n   
            in-ports       port       endpoint                        n                  axi          simple-bus                                    ‘                adc@f8007100             xlnx,zynq-xadc-1.00.a            8ø q              †                   ‘            <            can@e0008000             xlnx,zynq-can-1.0         	  #disabled             <            $        can_clk pclk             8à €             †                   ‘           *   @        8   @      can@e0009000             xlnx,zynq-can-1.0         	  #disabled             <            %        can_clk pclk             8à              †       3            ‘           *   @        8   @      gpio@e000a000            xlnx,zynq-gpio-1.0          F            <      *         R         b        w            ‘            †                   8à            i2c@e0004000             cdns,i2c-r1p10          #okay             <      &         ‘            †                   8à @                                 isl9305@68           isil,isl9305             8   h   regulators     dcd1             ¢VDD_DSP           ó      dcd2             ¢1P35V             ó      ldo1             ¢VDD_ADJ       ldo2          	   ¢VDD_GPIO              ó               i2c@e0005000             cdns,i2c-r1p10        	  #disabled             <      '         ‘            †       0            8à P                                    interrupt-controller@f8f01000            arm,cortex-a9-gic           w            b         8øð    øð             n         cache-controller@f8f02000            arm,pl310-cache          8øð              †                  ˆ                 ™                  ©        ·         memory-controller@f8006000           xlnx,zynq-ddrc-a05           8ø `          serial@e0000000          xlnx,xuartps cdns,uart-r1p8       	  #disabled             <            (        uart_clk pclk            8à               †                serial@e0001000          xlnx,xuartps cdns,uart-r1p8         #okay             <            )        uart_clk pclk            8à              †       2         spi@e0006000             xlnx,zynq-spi-r1p6           8à `          	  #disabled             ‘            †                   <            "        ref_clk pclk                                    spi@e0007000             xlnx,zynq-spi-r1p6           8à p          	  #disabled             ‘            †       1            <            #        ref_clk pclk                                    ethernet@e000b000            cdns,zynq-gem cdns,gem           8à °            #okay             †                   <                          pclk hclk tx_clk                                    	  Ãrgmii-id            Ì      ethernet-phy@0        4   ethernet-phy-id0141.0e90 ethernet-phy-ieee802.3-c22          8             ,ethernet-phy             ×        ÿ            ÿð   
         n            ethernet@e000c000            cdns,zynq-gem cdns,gem           8à À          	  #disabled             †       -            <                          pclk hclk tx_clk                                    memory-controller@e000e000        !   arm,pl353-smc-r2p1 arm,primecell             8à à          	  #disabled            memclk apb_pclk          <            ,      0           á             â             ä                                  nand-controller@0,0          arm,pl353-nand-r2p1          8                 	  #disabled                                       mmc@e0100000             arasan,sdhci-8.9a         	  #disabled            clk_xin clk_ahb          <                      ‘            †                   8à           mmc@e0101000             arasan,sdhci-8.9a           #okay            clk_xin clk_ahb          <            !         ‘            †       /            8à          slcr@f8000000                                  !   xlnx,zynq-slcr syscon simple-mfd             8ø                         n   	   clkc@100            è            xlnx,ps7-clkc           õ        j  armpll ddrpll iopll cpu_6or4x cpu_3or2x cpu_2x cpu_1x ddr2x ddr3x dci lqspi smc pcap gem0 gem1 fclk0 fclk1 fclk2 fclk3 can0 can1 sdio0 sdio1 uart0 uart1 spi0 spi1 dma usb0_aper usb1_aper gem0_aper gem1_aper sdio0_aper sdio1_aper spi0_aper spi1_aper can0_aper can1_aper i2c0_aper i2c1_aper uart0_aper uart1_aper gpio_aper lqspi_aper smc_aper swdt dbg_trc dbg_apb            8              ü U         n         rstc@200             xlnx,zynq-reset          8      H        %           2   	      pinctrl@700          xlnx,pinctrl-zynq            8              2   	         dmac@f8003000            arm,pl330 arm,primecell          8ø 0             ‘         .  9abort dma0 dma1 dma2 dma3 dma4 dma5 dma6 dma7         l   †                                                         (          )          *          +           I            <            	  apb_pclk          devcfg@f8007000          xlnx,zynq-devcfg-1.0             8ø p             ‘            †                   <              ref_clk         2   	         n         timer@f8f00200           arm,cortex-a9-global-timer           8øð              †                 ‘            <            timer@f8001000           ‘         $   †       
                             	   cdns,ttc             <               8ø           timer@f8002000           ‘         $   †       %          &          '         	   cdns,ttc             <               8ø            timer@f8f00600           ‘            †                 arm,cortex-a9-twd-timer          8øð              <            usb@e0002000          "   xlnx,zynq-usb-2.20a chipidea,usb2         	  #disabled             <               ‘            †                   8à              Tulpi          usb@e0003000          "   xlnx,zynq-usb-2.20a chipidea,usb2         	  #disabled             <               ‘            †       ,            8à 0            Tulpi          watchdog@f8005000            <      -         cdns,wdt-r1p2            ‘            †       	            8ø P            ]   
      etb@f8801000          "   arm,coresight-etb10 arm,primecell            8ø€             <            .      /        apb_pclk dbg_trc dbg_apb       in-ports       port       endpoint               
         n                  tpiu@f8803000         !   arm,coresight-tpiu arm,primecell             8ø€0             <            .      /        apb_pclk dbg_trc dbg_apb       in-ports       port       endpoint                        n                  funnel@f8804000       *   arm,coresight-static-funnel arm,primecell            8ø€@             <            .      /        apb_pclk dbg_trc dbg_apb       out-ports      port       endpoint                        n               in-ports                                 port@0           8       endpoint                        n            port@1           8      endpoint                        n            port@2           8      endpoint                   ptm@f889c000          "   arm,coresight-etm3x arm,primecell            8ø‰À             <            .      /        apb_pclk dbg_trc dbg_apb            i      out-ports      port       endpoint                        n                  ptm@f889d000          "   arm,coresight-etm3x arm,primecell            8ø‰Ð             <            .      /        apb_pclk dbg_trc dbg_apb            i      out-ports      port       endpoint                        n                     aliases         m/axi/ethernet@e000b000          w/axi/serial@e0001000          memory@0             ,memory           8    @         chosen        0  root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait         ˆserial0:115200n8             	#address-cells #size-cells compatible model device_type reg clocks clock-latency cpu0-supply operating-points phandle fpga-mgr ranges interrupts interrupt-parent regulator-name regulator-min-microvolt regulator-max-microvolt regulator-boot-on regulator-always-on clock-names remote-endpoint status tx-fifo-depth rx-fifo-depth #gpio-cells gpio-controller interrupt-controller #interrupt-cells arm,data-latency arm,tag-latency cache-unified cache-level phy-mode phy-handle marvell,reg-init #clock-cells fclk-enable clock-output-names ps-clk-frequency #reset-cells syscon interrupt-names #dma-cells phy_type timeout-sec cpu ethernet0 serial0 bootargs stdout-path 