  ث   8  ʹ   (            
  |                             1    google,krane-sku176 google,krane mediatek,mt8183                                     +            7MediaTek krane sku176 board    aliases          =/soc/i2c@11007000            B/soc/i2c@11011000            G/soc/i2c@11009000            L/soc/i2c@1100f000            Q/soc/i2c@11008000            V/soc/i2c@11016000            [/soc/i2c@11005000            `/soc/i2c@1101a000            e/soc/i2c@1101b000            j/soc/i2c@11014000            o/soc/i2c@11015000            u/soc/i2c@11017000            {/soc/ovl@14008000            /soc/ovl@14009000            /soc/ovl@1400a000            /soc/rdma@1400b000           /soc/rdma@1400c000           /soc/serial@11002000             /soc/mmc@11230000            /soc/mmc@11240000         opp-table-cluster0            operating-points-v2                           opp0-793000000               /D8@          	                  opp0-910000000               6=          
}                  opp0-1014000000              <pi          
                  opp0-1131000000              Ci                            opp0-1248000000              Jb           5                   opp0-1326000000              O	'          ~>                  opp0-1417000000              Tu@          P                  opp0-1508000000              YA           A            	      opp0-1586000000              ^p          6            
      opp0-1625000000              `ۈ@          
                  opp0-1677000000              c@          5                  opp0-1716000000              fH           f                  opp0-1781000000              j'@                            opp0-1846000000              n          B@                  opp0-1924000000              r                             opp0-1989000000              v@                               opp-table-cluster1            operating-points-v2                       #   opp1-793000000               /D8@          
`                  opp1-910000000               6=                            opp1-1014000000              <pi          q                  opp1-1131000000              Ci          X                  opp1-1248000000              Jb           5                   opp1-1326000000              O	'                            opp1-1417000000              Tu@          P                  opp1-1508000000              YA           Y            	      opp1-1586000000              ^p                      
      opp1-1625000000              `ۈ@          t                  opp1-1677000000              c@          5                  opp1-1716000000              fH           ~                  opp1-1781000000              j'@                            opp1-1846000000              n          B@                  opp1-1924000000              r                             opp1-1989000000              v@                               opp-table-cci             operating-points-v2                          opp-273000000                E@          	                  opp-338000000                %x          
}                  opp-403000000                J          
                  opp-463000000                                            opp-546000000                 L          5                   opp-624000000                %1|           ~>                  opp-689000000                )N@          P                  opp-767000000                -}          A            	      opp-845000000                2]@          6            
      opp-871000000                3g          
                  opp-923000000                7          5                  opp-962000000                9V          f                  opp-1027000000               =6                            opp-1092000000               A           B@                  opp-1144000000               D0                             opp-1196000000               GI                                cci           mediatek,mt8183-cci                               cci intermediate                                       !      cpus                         +       cpu-map    cluster0       core0                    core1                    core2                    core3                       cluster1       core0                    core1                    core2                    core3                          cpu@0           cpu           arm,cortex-a53          '            +psci            9          L                                     cpu intermediate                         \   T        v              !                             cpu@1           cpu           arm,cortex-a53          '           +psci            9          L                                     cpu intermediate                         \   T        v              !                             cpu@2           cpu           arm,cortex-a53          '           +psci            9          L                                     cpu intermediate                         \   T        v              !                             cpu@3           cpu           arm,cortex-a53          '           +psci            9          L                                     cpu intermediate                         \   T        v              !                             cpu@100         cpu           arm,cortex-a73          '           +psci            9           L      "                              cpu intermediate                #        \           v              !           $                  cpu@101         cpu           arm,cortex-a73          '          +psci            9           L      "                              cpu intermediate                #        \           v              !           $                  cpu@102         cpu           arm,cortex-a73          '          +psci            9           L      "                              cpu intermediate                #        \           v              !           $                  cpu@103         cpu           arm,cortex-a73          '          +psci            9           L      "                              cpu intermediate                #        \           v              !           $                  idle-states         psci       cpu-sleep             arm,idle-state                                                                        cluster-sleep-0           arm,idle-state                                                                     cluster-sleep-1           arm,idle-state                                                               "            opp-table-0           operating-points-v2                       l   opp-300000000                           	h P      opp-320000000                           	 P      opp-340000000                C           	< P      opp-360000000                u*           	Ҧ P      opp-380000000                W           	 P      opp-400000000                ׄ           
z P      opp-420000000                           
 P      opp-460000000                k           
L P      opp-500000000                e           
} P      opp-540000000                 /           
` P      opp-580000000                "           
4 P      opp-620000000                $s            P      opp-653000000                &@          YF P      opp-698000000                )           A      opp-743000000                ,IG           6      opp-800000000                /            H         pmu-a53           arm,cortex-a53-pmu              %                    &      pmu-a73           arm,cortex-a73-pmu              %                    '      psci              arm,psci-1.0            2smc       fixed-factor-clock-13m            fixed-factor-clock                          (                              &clk13m              5      oscillator            fixed-clock                     9        &clk26m              (      timer             arm,armv8-timer             %      @                                               
             soc                      +             simple-bus           I   efuse@8000000         %    mediatek,mt8183-efuse mediatek,efuse            '                                   +           Pokay          interrupt-controller@c000000              arm,gic-v3          W               %         h      P  '                                @              A             B                        	                }            %   ppi-partitions     interrupt-partition-0                                   &      interrupt-partition-1                                   '            syscon@c530000            mediatek,mt8183-mcucfg syscon           '    S                                      interrupt-controller@c530a80          .    mediatek,mt8183-sysirq mediatek,mt6577-sysirq            h        W               %        '    S
       P                  cpu-debug@d410000         &    arm,coresight-cpu-debug arm,primecell           '    A                     )   .      	   apb_pclk                     cpu-debug@d510000         &    arm,coresight-cpu-debug arm,primecell           '    Q                     )   .      	   apb_pclk                     cpu-debug@d610000         &    arm,coresight-cpu-debug arm,primecell           '    a                     )   .      	   apb_pclk                     cpu-debug@d710000         &    arm,coresight-cpu-debug arm,primecell           '    q                     )   .      	   apb_pclk                     cpu-debug@d810000         &    arm,coresight-cpu-debug arm,primecell           '                         )   .      	   apb_pclk                     cpu-debug@d910000         &    arm,coresight-cpu-debug arm,primecell           '                         )   .      	   apb_pclk                     cpu-debug@da10000         &    arm,coresight-cpu-debug arm,primecell           '                         )   .      	   apb_pclk                     cpu-debug@db10000         &    arm,coresight-cpu-debug arm,primecell           '                         )   .      	   apb_pclk                     syscon@10000000            mediatek,mt8183-topckgen syscon         '                                           syscon@10001000            mediatek,mt8183-infracfg syscon         '                                               )      syscon@10003000           mediatek,mt8183-pericfg syscon          '     0                               ]      pinctrl@10005000              mediatek,mt8183-pinctrl         '     P                                                                                                                                   D  iocfg0 iocfg1 iocfg2 iocfg3 iocfg4 iocfg5 iocfg6 iocfg7 iocfg8 eint                                *                    h                          W          SPI_AP_EC_CS_L SPI_AP_EC_MOSI SPI_AP_EC_CLK I2S3_DO USB_PD_INT_ODL     IT6505_HPD_L I2S3_TDM_D3 SOC_I2C6_1V8_SCL SOC_I2C6_1V8_SDA DPI_D0 DPI_D1 DPI_D2 DPI_D3 DPI_D4 DPI_D5 DPI_D6 DPI_D7 DPI_D8 DPI_D9 DPI_D10 DPI_D11 DPI_HSYNC DPI_VSYNC DPI_DE DPI_CK AP_MSDC1_CLK AP_MSDC1_DAT3 AP_MSDC1_CMD AP_MSDC1_DAT0 AP_MSDC1_DAT2 AP_MSDC1_DAT1       OTG_EN DRVBUS DISP_PWM DSI_TE LCM_RST_1V8 AP_CTS_WIFI_RTS AP_RTS_WIFI_CTS SOC_I2C5_1V8_SCL SOC_I2C5_1V8_SDA SOC_I2C3_1V8_SCL SOC_I2C3_1V8_SDA                              SOC_I2C1_1V8_SDA SOC_I2C0_1V8_SDA SOC_I2C0_1V8_SCL SOC_I2C1_1V8_SCL AP_SPI_H1_MISO AP_SPI_H1_CS_L AP_SPI_H1_MOSI AP_SPI_H1_CLK I2S5_BCK I2S5_LRCK I2S5_DO BOOTBLOCK_EN_L MT8183_KPCOL0 SPI_AP_EC_MISO UART_DBG_TX_AP_RX UART_AP_TX_DBG_RX I2S2_MCK I2S2_BCK CLK_5M_WCAM CLK_2M_UCAM I2S2_LRCK I2S2_DI SOC_I2C2_1V8_SCL SOC_I2C2_1V8_SDA SOC_I2C4_1V8_SCL SOC_I2C4_1V8_SDA  SCL8 SDA8 FCAM_PWDN_L                          I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC       AP_FLASH_WP_L EC_AP_INT_ODL IT6505_INT_ODL H1_INT_OD_L        AP_SPI_FLASH_MISO AP_SPI_FLASH_CS_L AP_SPI_FLASH_MOSI AP_SPI_FLASH_CLK DA7219_IRQ                                        *   audiopins                  pins-bus          D    a  b  e  f    Y  Z  [                           audiotdmouton                  pins-bus                        
                    audiotdmoutoff                 pins-bus                             
                                       bt-pins             @   pins-bt-en            x          '         ec-ap-int-odl               V   pins1                                2         h1-int-od-l             K   pins1                                i2c0                C   pins-bus              R  S        ?           T             i2c1                T   pins-bus              Q  T        ?           T             i2c2                G   pins-bus              g  h         p        T             i2c3                R   pins-bus              2  3        ?           T             i2c4                E   pins-bus              i  j         p        T             i2c5                X   pins-bus              0  1        ?           T             i2c6                B   pins-bus                         p         mmc0-pins-default               a   pins-cmd-dat          $    {    }    ~        z                            ?         pins-clk              |                   }   
      pins-rst                                 }            mmc0-pins-uhs               b   pins-cmd-dat          $    {    }    ~        z                            ?         pins-clk              |                   }   
      pins-ds                              }   
      pins-rst                                 ?            mmc1-pins-default               e   pins-cmd-dat                   "  !                   ?   
      pins-clk                               }   
         mmc1-pins-uhs               f   pins-cmd-dat                   "  !                              ?   
      pins-clk                                 }   
                  panel-pins-default              p   panel-reset           -          '         2         pwm0-pin-default                Q   pins1                                2      pins2             +         scp             4   pins-scp-uart             n  p         spi0                J   pins-spi              U  V   W  X         p         spi1                S   pins-spi                             p         spi2                U   pins-spi                            p      pins-spi-mi           ^        }             spi3                W   pins-spi                             p         spi4                Y   pins-spi                             p         spi5                Z   pins-spi                             p         uart0-pins-default              =   pins-rx           _                  2      pins-tx           `         uart1-pins-default              >   pins-rx           y                  2      pins-tx           s      pins-rts              /               pins-cts              .                  uart1-pins-sleep                ?   pins-rx           y                   2      pins-tx           s      pins-rts              /               pins-cts              .                  wifi-pins-pwrseq                   pins-wifi-enable              w          '         wifi-pins-wakeup                   pins-wifi-wakeup              q                   ppvarp-lcd-en                  pins1             B          '         ppvarn-lcd-en                  pins1                       '         pp1800-lcd-en                  pins1             $          '         open_touch              D   irq_pin                              2      rst_pin                                 syscon@10006000       )    mediatek,mt8183-scpsys syscon simple-mfd            '     `           power-controller          !    mediatek,mt8183-power-controller                         +                           P   power-domain@0          '                      )   /   )   7         audio audio1 audio2                   power-domain@1          '              )                  power-domain@2          '                           mfg                      +                          +   power-domain@3          '                        +                          ,   power-domain@4          '                     power-domain@5          '                     power-domain@6          '              )                        power-domain@7          '         X            -       -      -      -      -      -      -      -      -      -   	      5   mm mm-0 mm-1 mm-2 mm-3 mm-4 mm-5 mm-6 mm-7 mm-8 mm-9               )           .                     +                  power-domain@8          '         @            /       /   	   /      /      /      /      /         .   cam cam-0 cam-1 cam-2 cam-3 cam-4 cam-5 cam-6              )           .                  power-domain@9          '   	               "   0   	   0            isp isp-0 isp-1            )           .                  power-domain@10         '   
           .                  power-domain@11         '              .                  power-domain@12         '         @         &      #   1       1      1      1      1      1         -   vpu vpu1 vpu-0 vpu-1 vpu-2 vpu-3 vpu-4 vpu-5               )           .                     +                  power-domain@13         '                  $         vpu2               )                  power-domain@14         '                  %         vpu3               )                              watchdog@10007000             mediatek,mt8183-wdt         '     p                               _      syscon@1000c000       "    mediatek,mt8183-apmixedsys syscon           '                                    O      pwrap@1000d000            mediatek,mt8183-pwrap           '                     pwrap                                    )   )         	   spi wrap       mt6358            mediatek,mt6358          h            *                      W      mt6358codec           mediatek,mt6358-sound                          2      mt6358regulator           mediatek,mt6358-regulator      buck_vdram1         vdram1                    5 L        M  0        b             ~                     buck_vcore          vcore                     5         M  j        b            ~                     buck_vpa            vpa                   5 7        M  P        b                        buck_vproc11            vproc11                   5         M  j        b            ~                           $      buck_vproc12            vproc12                   5         M  j        b            ~                                 buck_vgpu           vgpu                      5         M  j        b                              ,      buck_vs2            vs2                   5 L        M  0        b             ~      buck_vmodem         vmodem                    5         M  j        b           ~                     buck_vs1            vs1          B@        5 '{l        M  0        b             ~      ldo_vdram2          vdram2           	'        5 w@        b           ~      ldo_vsim1           vsim1            )2        5 )2        b        ldo_vibr            vibr             O        5 2Z        b   <      ldo_vrf12             regulator-fixed         vrf12            O        5 O        b   x      ldo_vio18             regulator-fixed         vio18            w@        5 w@        b  
         ~            d      ldo_vusb            vusb             -        5 /M`        b           ~            ^      ldo_vcamio            regulator-fixed         vcamio           w@        5 w@        b  E            H      ldo_vcamd           vcamd                    5 w@        b  E      ldo_vcn18             regulator-fixed         vcn18            w@        5 w@        b              F      ldo_vfe28             regulator-fixed         vfe28            *        5 *        b        ldo_vsram_proc11            vsram_proc11                      5         M  j        b            ~      ldo_vcn28             regulator-fixed         vcn28            *        5 *        b        ldo_vsram_others            vsram_others                      5         M  j        b            ~      ldo_vsram_gpu         
  vsram_gpu                     5         M  j        b               +      ldo_vxo22             regulator-fixed         vxo22            !        5 !        b   x         ~      ldo_vefuse          vefuse                   5         b        ldo_vaux18            regulator-fixed         vaux18           w@        5 w@        b        ldo_vmch            vmch             ,@         5 2Z        b   <      ldo_vbif28            regulator-fixed         vbif28           *        5 *        b        ldo_vsram_proc12            vsram_proc12                      5         M  j        b            ~      ldo_vcama1          vcama1           w@        5 -        b  E      ldo_vemc            vemc             ,@         5 2Z        b   <            c      ldo_vio28             regulator-fixed         vio28            *        5 *        b        ldo_va12              regulator-fixed         va12             O        5 O        b           ~      ldo_vrf18             regulator-fixed         vrf18            w@        5 w@        b   x      ldo_vcn33_bt          	  vcn33_bt             2Z        5 5g        b        ldo_vcn33_wifi          vcn33_wifi           2Z        5 5g        b        ldo_vcama2          vcama2           *        5 *        b  E            I      ldo_vmc         vmc          w@        5 2Z        b   <      ldo_vldo28          vldo28           *        5 -        b        ldo_vaud28            regulator-fixed         vaud28           *        5 *        b              2      ldo_vsim2           vsim2            )2        5 )2        b           mt6358rtc             mediatek,mt6358-rtc       mt6358keys            mediatek,mt6358-keys       power              t               home               f               keyboard@10010000             mediatek,mt6779-keypad          '                                           (         kpd       	  Pdisabled          scp@10500000              mediatek,mt8183-scp          '    P             \             	  sram cfg                                  )            main               3        Pokay            default            4   cros_ec           google,cros-ec-rpmsg            cros-ec-rpmsg            timer@10017000        ,    mediatek,mt8183-timer mediatek,mt6765-timer         '    p                                      5      iommu@10205000            mediatek,mt8183-m4u         '     P                                     6   7   8   9   :   ;   <                       n      mailbox@10238000              mediatek,mt8183-gce         '    #       @                                          )            gce             m      auxadc@11001000       .    mediatek,mt8183-auxadc mediatek,mt8173-auxadc           '                         )   #         main            )           Pokay                N      serial@11002000       *    mediatek,mt8183-uart mediatek,mt6577-uart           '                             [               (   )         	   baud bus            Pokay            default            =      serial@11003000       *    mediatek,mt8183-uart mediatek,mt6577-uart           '     0                       \               (   )         	   baud bus            Pokay            default sleep              >        ;   ?        E          \      *   y      bluetooth           default            @        Pokay              qcom,qca6174-bt         Y   *   x                A        fnvm_00440302_i2s_eu.bin          serial@11004000       *    mediatek,mt8183-uart mediatek,mt6577-uart           '     @                       ]               (   )         	   baud bus          	  Pdisabled          i2c@11005000              mediatek,mt8183-i2c          '     P                                    W               )   W   )   *      	   main dma                                    +            Pokay            default            B        9       i2c@11007000              mediatek,mt8183-i2c          '     p                                    Q               )   
   )   *      	   main dma                                    +            Pokay            default            C        9    touchscreen@5d            hid-over-i2c            '   ]        default            D            *                      t   
                    i2c@11008000              mediatek,mt8183-i2c          '                                         R               )      )   *   )   G         main dma arb                                    +            Pokay            default            E        9            F   eeprom@54             atmel,24c32         '   T                       F         i2c@11009000              mediatek,mt8183-i2c          '                                        S               )      )   *   )   I         main dma arb                                    +            Pokay            default            G        9            H   eeprom@58             atmel,24c32         '   X                       I         spi@1100a000              mediatek,mt8183-spi                      +            '                            x                  6         )            parent-clk sel-clk spi-clk          Pokay            default            J                       *   V      cr50@0            google,cr50         '             B@        default            K            *                       svs@1100b000              mediatek,mt8183-svs         '                                           )   	         main               L   M      (  svs-calibration-data t-calibration-data       thermal@1100b000                         mediatek,mt8183-thermal         '                         )   	   )   #         therm auxadc               )                   L           #   N        3   O           M        calibration-data                y      pwm@1100e000              mediatek,mt8183-disp-pwm            '                                       G   P           U                     )   5         main mm         Pokay            default            Q            }      pwm@11006000              mediatek,mt8183-pwm         '     `                U         0      )      )      )      )      )      )            top main pwm1 pwm2 pwm3 pwm4          i2c@1100f000              mediatek,mt8183-i2c          '                                         T               )      )   *      	   main dma                                    +            Pokay            default            R        9       spi@11010000              mediatek,mt8183-spi                      +            '                            |                  6         )   8         parent-clk sel-clk spi-clk          Pokay            default            S               flash@0           winbond,w25q64dw jedec,spi-nor          '            }x@         i2c@11011000              mediatek,mt8183-i2c          '                                       U               )   9   )   *      	   main dma                                    +            Pokay            default            T        9       spi@11012000              mediatek,mt8183-spi                      +            '                                              6         )   ;         parent-clk sel-clk spi-clk          Pokay            default            U               cros-ec@0             google,cros-ec-spi          '             -            *                      default            V   i2c-tunnel            google,cros-ec-i2c-tunnel           `                        +       sbs-battery@b             sbs,sbs-battery         '           r                       extcon0           google,extcon-usbc-cros-ec                    typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         '            dual            host            sink             cbas              google,cros-cbas          keyboard-controller           google,cros-ec-keyb-switches                spi@11013000              mediatek,mt8183-spi                      +            '    0                                         6         )   <         parent-clk sel-clk spi-clk        	  Pdisabled            default            W                  i2c@11014000              mediatek,mt8183-i2c          '    @                                                  )   H   )   *   )   G         main dma arb                                    +          	  Pdisabled          i2c@11015000              mediatek,mt8183-i2c          '    P                                                   )   J   )   *   )   I         main dma arb                                    +          	  Pdisabled          i2c@11016000              mediatek,mt8183-i2c          '    `                                    V               )   D   )   *   )   E         main dma arb                                    +            Pokay            default            X        9       i2c@11017000              mediatek,mt8183-i2c          '    p                                                  )   F   )   *   )   E         main dma arb                                    +          	  Pdisabled          spi@11018000              mediatek,mt8183-spi                      +            '                                             6         )   K         parent-clk sel-clk spi-clk        	  Pdisabled            default            Y                  spi@11019000              mediatek,mt8183-spi                      +            '                                             6         )   L         parent-clk sel-clk spi-clk        	  Pdisabled            default            Z                  i2c@1101a000              mediatek,mt8183-i2c          '                                       X               )   b   )   *      	   main dma                                    +          	  Pdisabled          i2c@1101b000              mediatek,mt8183-i2c          '                                        Y               )   c   )   *      	   main dma                                    +          	  Pdisabled          usb@11201000          #    mediatek,mt8183-mtu3 mediatek,mtu3           '            .      >              	  mac ippc                   H              [      \               )   =   )   Z         sys_ck ref_ck              ]      e                     +            I        Pokay            host                        ^   usb@11200000          '    mediatek,mt8183-xhci mediatek,mtk-xhci          '                      mac                I               )   =   )   Z         sys_ck ref_ck           Pokay                         +               ^   hub@1             usb5e3,610          '               audio-controller@11220000              mediatek,mt8183-audiosys syscon         '    "                                `   mt8183-afe-pcm            mediatek,mt8183-audio                                _         	  audiosys            G   P         D      `      `      `      `      `      `      `      `      `      `      `      `   
   `   	   `      `       )   /   )   7                  0            H            L            K            O      t      u      v      w      x      y      z      {      |      }      ~         (     w   aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adc_adda6_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_i2s1_bclk_sw aud_i2s2_bclk_sw aud_i2s3_bclk_sw aud_i2s4_bclk_sw aud_tdm_clk aud_tml_clk aud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_aud_intbus top_syspll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_clk26m_clk          I2S2            I2S5                         mmc@11230000              mediatek,mt8183-mmc          '    #                                     M                     )      )            source hclk source_cg           Pokay            default state_uhs              a        ;   b        &                     0         B         Q         `         q         y         (           c           d                            U               mmc@11240000              mediatek,mt8183-mmc          '    $                                     N                  	   )      )   (         source hclk source_cg           Pokay            default state_uhs              e        ;   f           g           h           i        &                                                                             2                  ?         y              	              V                     +       qca-wifi@1            qcom,ath10k         '         	  FLE_Krane             dsi-phy@11e50000              mediatek,mt8183-mipi-tx         '                         O                       f            &mipi_tx0_pll               j        calibration-data            Pokay                o      efuse@11f10000        %    mediatek,mt8183-efuse mediatek,efuse            '                                  +      calib@180           '                 M      calib@190           '                 j      calib@580           '     d            L         t-phy@11f40000        .    mediatek,mt8183-tphy mediatek,generic-tphy-v2                        +           I                     Pokay       usb-phy@0           '                   (         ref         f           q           Pokay                [      usb-phy@700         '     	             (         ref         f           Pokay                \         syscon@13000000           mediatek,mt8183-mfgcfg syscon           '                                 G   P               k      gpu@13040000          &    mediatek,mt8183-mali arm,mali-bifrost           '            @       $                                     job mmu gpu             k            G   P      P      P           core0 core1 core2               l           ,           +      syscon@14000000           mediatek,mt8183-mmsys syscon            '                                               m          m                 m                      -      dma-controller0@14001000              mediatek,mt8183-mdp3-rdma           '                        m                               G   P               -      -              n               m              m                            mdp3-rsz0@14003000            mediatek,mt8183-mdp3-rsz            '     0                   m     0                              -         mdp3-rsz1@14004000            mediatek,mt8183-mdp3-rsz            '     @                   m     @                              -         dma-controller@14005000           mediatek,mt8183-mdp3-wrot           '     P                   m     P                  !        G   P               -              n                    mdp3-wdma@14006000            mediatek,mt8183-mdp3-wdma           '     `                   m     `                  "        G   P               -   )           n         ovl@14008000              mediatek,mt8183-disp-ovl            '                                       G   P               -              n               m               ovl@14009000              mediatek,mt8183-disp-ovl-2l         '                                       G   P               -              n              m               ovl@1400a000              mediatek,mt8183-disp-ovl-2l         '                                       G   P               -              n              m               rdma@1400b000             mediatek,mt8183-disp-rdma           '                                       G   P               -              n           	              m               rdma@1400c000             mediatek,mt8183-disp-rdma           '                                       G   P               -              n           	              m               color@1400e000        6    mediatek,mt8183-disp-color mediatek,mt8173-disp-color           '                                       G   P               -              m               ccorr@1400f000            mediatek,mt8183-disp-ccorr          '                                       G   P               -              m               aal@14010000              mediatek,mt8183-disp-aal            '                                       G   P               -              m                gamma@14011000            mediatek,mt8183-disp-gamma          '                                      G   P               -              m               dither@14012000           mediatek,mt8183-disp-dither         '                                       G   P               -              m                dsi@14014000              mediatek,mt8183-dsi         '    @                                  G   P               -      -       o         engine digital hs              -              o        	dphy            Pokay                         +       panel@0         '            Y   *   -            default            p        	#   q        	/   r        	;   s        	I   t        	S          Pokay              boe,tv101wum-nl6       port       endpoint            	\   u            v            ports      port       endpoint            	\   v            u               mutex@14016000            mediatek,mt8183-disp-mutex          '    `                                  G   P                            m     `          larb@14017000             mediatek,mt8183-smi-larb            '    p                   .            -      -           G   P            apb smi             6      smi@14019000              mediatek,mt8183-smi-common          '                         -       -       -      -            apb smi gals0 gals1         G   P               .      mdp3-ccorr@1401c000           mediatek,mt8183-mdp3-ccorr          '                       m                       1            -   +      syscon@15020000           mediatek,mt8183-imgsys syscon           '                                    0      larb@15021000             mediatek,mt8183-smi-larb            '                       .            0   	   0   	   -            apb smi gals            G   P   	            ;      larb@1502f000             mediatek,mt8183-smi-larb            '                       .            0      0      -   	         apb smi gals            G   P   	            8      syscon@16000000           mediatek,mt8183-vdecsys syscon          '                                     w      larb@16010000             mediatek,mt8183-smi-larb            '                        .            w       w            apb smi         G   P   
            7      syscon@17000000           mediatek,mt8183-vencsys syscon          '                                     x      larb@17010000             mediatek,mt8183-smi-larb            '                        .            x       x             apb smi         G   P               :      venc_jpg@17030000         +    mediatek,mt8183-jpgenc mediatek,mtk-jpgenc          '                                          n      n           G   P               x            jpgenc        syscon@19000000            mediatek,mt8183-ipu_conn syscon         '                                     1      syscon@19010000           mediatek,mt8183-ipu_adl syscon          '                              syscon@19180000       !    mediatek,mt8183-ipu_core0 syscon            '                              syscon@19280000       !    mediatek,mt8183-ipu_core1 syscon            '    (                          syscon@1a000000           mediatek,mt8183-camsys syscon           '                                     /      larb@1a001000             mediatek,mt8183-smi-larb            '                        .            /       /       -            apb smi gals            G   P               <      larb@1a002000             mediatek,mt8183-smi-larb            '                         .            /   	   /   	   -            apb smi gals            G   P               9         thermal-zones      cpu-thermal         	l   d        	          	   y            	     trips      trip-point0         	 	        	          "passive       trip-point1         	 8        	          "passive             z      cpu-crit            	 8        	        	  "critical             cooling-maps       map0            	   z      0  	                    	         map1            	   z      0  	                    	               tzts1           	l            	            	   y           	     trips         cooling-maps             tzts2           	l            	            	   y           	     trips         cooling-maps             tzts3           	l            	            	   y           	     trips         cooling-maps             tzts4           	l            	            	   y           	     trips         cooling-maps             tzts5           	l            	            	   y           	     trips         cooling-maps             tztsABB         	l            	            	   y           	     trips         cooling-maps             tboard1         	          	l            	   {      tboard2         	          	l            	   |         chosen          	serial0:115200n8          backlight_lcd0            pwm-backlight           	   }              	   ~        Y   *               
              
          
1  @        Pokay                t      memory@40000000         memory          '    @                oscillator1           fixed-clock                     9           &clk32k              A      regulator0            regulator-fixed         it6505_pp18          w@        5 w@        
J   *                
O      regulator1            regulator-fixed         lcd_pp3300           2Z        5 2Z         ~         
b      regulator2            regulator-fixed       
  bl_pp5000            LK@        5 LK@         ~         
b            ~      regulator3            regulator-fixed         mmc1_power           2Z        5 2Z            g      regulator4            regulator-fixed         mmc1_io          w@        5 w@            h      regulator5            regulator-fixed         pp1800_alw           ~         
b         w@        5 w@      regulator6            regulator-fixed         pp3300_alw           ~         
b         2Z        5 2Z      reserved-memory                      +            I   memory@50000000           shared-dma-pool         '    P                  
t            3         mt8183-sound            
{         '  default aud_tdm_out_on aud_tdm_out_off                     ;           
           Pokay          (    mediatek,mt8183_mt6358_ts3a227_max98357       bt-sco            linux,bt-sco          wifi-pwrseq           mmc-pwrseq-simple           default                    
   *   w               i      wifi-wakeup       
    gpio-keys           default               button-wowlan           
Wake on WiFi            `   *   q            
                     thermal-sensor1           generic-adc-thermal                     
   N            
sensor-channel          
x              '  .  :    N   l  a    u0      7  @      {  P  (      `      a p  / $   8    L    _    s       y (   h    Z 8   N    C H   ;            {      thermal-sensor2           generic-adc-thermal                     
   N           
sensor-channel          
x              '  .  :    N   l  a    u0      7  @      {  P  (      `      a p  / $   8    L    _    s       y (   h    Z 8   N    C H   ;            |      max98357a             maxim,max98357a         
   *             ppvarn-lcd            regulator-fixed         ppvarn_lcd          default                     
O        
J   *   B                q      ppvarp-lcd            regulator-fixed         ppvarp_lcd          default                     
O        
J   *                   r      pp1800-lcd            regulator-fixed         pp1800_lcd          default                     
O        
J   *   $                s         	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 i2c7 i2c8 i2c9 i2c10 i2c11 ovl0 ovl-2l0 ovl-2l1 rdma0 rdma1 serial0 mmc0 mmc1 opp-shared phandle opp-hz opp-microvolt required-opps clocks clock-names operating-points-v2 proc-supply cpu device_type reg enable-method capacity-dmips-mhz cpu-idle-states dynamic-power-coefficient #cooling-cells mediatek,cci entry-method local-timer-stop arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us interrupts #clock-cells clock-div clock-mult clock-output-names clock-frequency ranges status #interrupt-cells interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux drive-strength input-enable bias-pull-down output-low bias-pull-up mediatek,pull-up-adv mediatek,drive-strength-adv bias-disable mediatek,pull-down-adv output-high output-enable #power-domain-cells mediatek,infracfg domain-supply mediatek,smi mediatek,dmic-mode Avdd-supply regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-always-on regulator-allowed-modes linux,keycodes wakeup-source memory-region pinctrl-names pinctrl-0 mediatek,rpmsg-name mediatek,larbs #iommu-cells #mbox-cells #io-channel-cells pinctrl-1 interrupts-extended enable-gpios firmware-name post-power-on-delay-ms hid-descr-addr vbus-supply pagesize vcc-supply mediatek,pad-select cs-gpios spi-max-frequency nvmem-cells nvmem-cell-names #thermal-sensor-cells resets mediatek,auxadc mediatek,apmixedsys power-domains #pwm-cells google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count google,usb-port-id power-role data-role try-power-role phys mediatek,syscon-wakeup dr_mode vusb33-supply reset-names i2s3-share i2s0-share bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply assigned-clocks assigned-clock-parents non-removable mmc-pwrseq drv-type cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 keep-power-in-suspend cap-sdio-irq no-mmc qcom,ath10k-calibration-variant #phy-cells mediatek,discth interrupt-names power-domain-names mali-supply sram-supply mboxes mediatek,gce-client-reg mediatek,gce-events iommus #dma-cells mediatek,rdma-fifo-size phy-names avdd-supply avee-supply pp1800-supply backlight rotation remote-endpoint polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution stdout-path pwms power-supply brightness-levels num-interpolated-steps default-brightness-level gpio enable-active-high regulator-boot-on no-map mediatek,platform pinctrl-2 reset-gpios label linux,code io-channels io-channel-names temperature-lookup-table sdmode-gpios 