     8      (                                           %    mediatek,mt8195-demo mediatek,mt8195                                     +            7MediaTek MT8195 demo board     aliases          =/soc/mailbox@10320000            B/soc/mailbox@10330000            G/soc/serial@11001100          cpus                         +       cpu@0            Ocpu           arm,cortex-a55           [             _psci             m                ec3@           4                                                   	      cpu@100          Ocpu           arm,cortex-a55           [            _psci             m                ec3@           4                                                   
      cpu@200          Ocpu           arm,cortex-a55           [            _psci             m                ec3@           4                                                         cpu@300          Ocpu           arm,cortex-a55           [            _psci             m                ec3@           4                                                         cpu@400          Ocpu           arm,cortex-a78           [            _psci             m               f                                                                     cpu@500          Ocpu           arm,cortex-a78           [            _psci             m               f                                                                     cpu@600          Ocpu           arm,cortex-a78           [            _psci             m               f                                                                     cpu@700          Ocpu           arm,cortex-a78           [            _psci             m               f                                                                     cpu-map    cluster0       core0               	      core1               
      core2                     core3                     core4                     core5                     core6                     core7                           idle-states          psci       cpu-off-l             arm,idle-state                                 2        &   _        6  D                  cpu-off-b             arm,idle-state                                 -        &           6                    cluster-off-l             arm,idle-state                                7        &           6  H                  cluster-off-b             arm,idle-state                                2        &           6                       l2-cache0             cache                                 l2-cache1             cache                                 l3-cache              cache                        dsu-pmu           arm,dsu-pmu         G                       R   	   
                          Wfail          dmic-codec            dmic-codec          ^           k   2      mt8195-sound            {         	  Wdisabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m              (      oscillator-26m            fixed-clock                              clk26m                    oscillator-32k            fixed-clock                                 clk32k        performance-controller@11bc10             mediatek,cpufreq-hw           [                 0                                    pmu-a55           arm,cortex-a55-pmu                      G                  pmu-a78           arm,cortex-a78-pmu                      G                  psci              arm,psci-1.0             fsmc       timer             arm,armv8-timer                   @  G                                             
             soc                      +             simple-bus              interrupt-controller@c000000              arm,gic-v3                                                       [                                    G      	                      ppi-partitions     interrupt-partition-0           '   	   
                        interrupt-partition-1           '                                    syscon@10000000            mediatek,mt8195-topckgen syscon          [                                           syscon@10001000       .    mediatek,mt8195-infracfg_ao syscon simple-mfd            [                                0                     syscon@10003000           mediatek,mt8195-pericfg syscon           [     0                               2      pinctrl@10005000              mediatek,mt8195-pinctrl          [     P                                                                                                         B  =iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            G        W           c                               G                                        gpio-keys-pins              x   pins            o  j          v         i2c6-pins               A   pins            o                      mmc0-default-pins               5   pins-clk            o  z                      f      pins-cmd-dat          $  o  ~  }  |  {  w  v  u  t  y         v                      e      pins-rst            o  x                      e         mmc0-uhs-pins               6   pins-clk            o  z                      f      pins-cmd-dat          $  o  ~  }  |  {  w  v  u  t  y         v                      e      pins-ds         o                        f      pins-rst            o  x                      e         mmc1-default-pins               9   pins-clk            o  o                      f      pins-cmd-dat            o  n  p  q  r  s         v                      e      pins-insert         o                     mmc1-uhs-pins               :   pins-clk            o  o                      f      pins-cmd-dat            o  n  p  q  r  s         v                      e         uart0-pins              .   pins            o  b  c         uart1-pins              /   pins            o  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd             [     `           power-controller          !    mediatek,mt8195-power-controller                         +                           *   power-domain@8           [                        +                  power-domain@9           [   	                      mfg                                 +                  power-domain@10          [   
                  power-domain@11          [                     power-domain@12          [                     power-domain@13          [                     power-domain@14          [                           power-domain@15          [                                   	      @      A      K                                                                                                                                vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +                  power-domain@24          [                          vdec1-0                              power-domain@27          [                          venc1-larb                               power-domain@16          [         8              $      %      &      '      (      )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +                  power-domain@17          [                                     vppsys1 vppsys1-0 vppsys1-1                              power-domain@22          [                                          $  wepsys-0 wepsys-1 wepsys-2 wepsys-3                              power-domain@23          [                           vdec0-0                              power-domain@25          [              !            vdec2-0                              power-domain@26          [              "            venc0-larb                               power-domain@18          [                     #       #      #         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +                  power-domain@19          [                                power-domain@20          [                                power-domain@21          [                 Q        hdmi_tx                      power-domain@28          [              $       $   
        img-0 img-1                                 +                  power-domain@29          [                     power-domain@30          [                    $      %           ipe ipe-0 ipe-1                                 power-domain@31          [         (     &       &      &      &      &           cam-0 cam-1 cam-2 cam-3 cam-4                                   +                  power-domain@32          [                      power-domain@33          [   !                  power-domain@34          [   "                           power-domain@0           [                                 power-domain@1           [                                power-domain@2           [                     power-domain@3           [                     power-domain@4           [                 5      7        csi_rx_top csi_rx_top1                    power-domain@5           [              '           ether                     power-domain@6           [                 X      n        adsp adsp1                       +                             power-domain@7           [                  g      "      n      2        audio audio1 audio2 audio3                                        watchdog@10007000             mediatek,mt8195-wdt                   [     p                0               -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon            [                                          timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer          [    p                G      	                  (      pwrap@10024000            mediatek,mt8195-pwrap syscon             [    @                =pwrap           G                                         	  spi wrap                  $                 pmic              mediatek,mt6359                                         mt6359codec       regulators     buck_vs1            3vs1         B 5         Z !        r                   buck_vgpu11         3vgpu11          B         Z 7                  r                                    buck_vmodem         3vmodem          B         Z           *        r         buck_vpu            3vpu         B         Z 7                  r                                    buck_vcore          3vcore           B         Z                    r                                    buck_vs2            3vs2         B 5         Z j         r                   buck_vpa            3vpa         B          Z 7        r  ,      buck_vproc2         3vproc2          B         Z 7          L        r                                    buck_vproc1         3vproc1          B         Z 7          L        r                                    buck_vcore_sshub            3vcore_sshub         B         Z 7      buck_vgpu11_sshub           3vgpu11_sshub            B         Z 7      ldo_vaud18          3vaud18          B w@        Z w@        r         ldo_vsim1           3vsim1           B         Z /M`      ldo_vibr            3vibr            B O        Z 2Z      ldo_vrf12           3vrf12           B         Z                 ldo_vusb            3vusb            B -        Z -        r                       3      ldo_vsram_proc2         3vsram_proc2         B          Z           L        r                  ldo_vio18           3vio18           B         Z         r                 ldo_vcamio          3vcamio          B         Z       ldo_vcn18           3vcn18           B w@        Z w@        r         ldo_vfe28           3vfe28           B *        Z *        r   x      ldo_vcn13           3vcn13           B         Z        ldo_vcn33_1_bt          3vcn33_1_bt          B *        Z 5g      ldo_vcn33_1_wifi            3vcn33_1_wifi            B *        Z 5g      ldo_vaux18          3vaux18          B w@        Z w@        r                  ldo_vsram_others            3vsram_others            B          Z                   r                  ldo_vefuse          3vefuse          B         Z       ldo_vxo22           3vxo22           B w@        Z !               ldo_vrfck           3vrfck           B `        Z       ldo_vrfck_1         3vrfck           B         Z j       ldo_vbif28          3vbif28          B *        Z *        r         ldo_vio28           3vio28           B *        Z 2Z               ldo_vemc            3vemc            B ,@         Z 2Z      ldo_vemc_1          3vemc            B &%        Z 2Z            7      ldo_vcn33_2_bt          3vcn33_2_bt          B *        Z 5g      ldo_vcn33_2_wifi            3vcn33_2_wifi            B *        Z 5g      ldo_va12            3va12            B O        Z                 ldo_va09            3va09            B 5         Z O      ldo_vrf18           3vrf18           B         Z P      ldo_vsram_md          	  3vsram_md            B          Z           *        r                  ldo_vufs            3vufs            B         Z             8      ldo_vm18            3vm18            B         Z                ldo_vbbck           3vbbck           B         Z O               ldo_vsram_proc1         3vsram_proc1         B          Z           L        r                  ldo_vsim2           3vsim2           B         Z /M`      ldo_vsram_others_sshub          3vsram_others_sshub          B          Z          mt6359rtc             mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi              [    p                            =pmif spmimst                               E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                    infra-iommu@10315000              mediatek,mt8195-iommu-infra          [    1P       P       P  G                                                                                  mailbox@10320000              mediatek,mt8195-gce          [    2        @         G                                                   h      mailbox@10330000              mediatek,mt8195-gce          [    3        @         G                                             scp@10500000              mediatek,mt8195-scp       0   [    P             r             p                 =sram cfg l1tcm          G                   	  Wdisabled          clock-controller@10720000             mediatek,mt8195-scp_adsp             [    r                                )      dsp@10803000              mediatek,mt8195-dsp           [    0                           	  =cfg sram          ,        X         n         )          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             *           rx tx              +   ,      	  Wdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox                        [    `                G                         +      mailbox@10817000              mediatek,mt8195-adsp-mbox                        [    p                G                         ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio            [                                   *           G      6                  -         	  !audiosys                                                               g      "      #      n      e      a      b      c      d      2   )            clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  Wdisabled                      serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                     	  baud bus            Wokay            -default         ;   .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                     	  baud bus            Wokay            -default         ;   /      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                     	  baud bus          	  Wdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                    	  baud bus          	  Wdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                    	  baud bus          	  Wdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                    	  baud bus          	  Wdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc            [                                    main            E         	  Wdisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon            [     0                               '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                     G                                                parent-clk sel-clk spi-clk        	  Wdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                     G                                        3        parent-clk sel-clk spi-clk        	  Wdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                     G                                        4        parent-clk sel-clk spi-clk        	  Wdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [    0                G                                        5        parent-clk sel-clk spi-clk        	  Wdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                    G                                        <        parent-clk sel-clk spi-clk        	  Wdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                    G                                        =        parent-clk sel-clk spi-clk        	  Wdisabled          spi@1101d000              mediatek,mt8195-spi-slave            [                    G                            R        spi                                   	  Wdisabled          spi@1101e000              mediatek,mt8195-spi-slave            [                    G                            S        spi                                   	  Wdisabled          usb@11200000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            [                   >              	  =mac ippc            G                      W   0      1                 ,      -                          $        /                     B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         \   2      g         s        Wokay               3           4      mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           [    #                              G                                                source hclk source_cg           Wokay            -default state_uhs           ;   5           6                                                                                   L           7        '   8         4      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           [    $                              G                                        $        source hclk source_cg                                       Wokay            -default state_uhs           ;   9           :        B                                      K         \         i           ;        '   <      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           [    %                              G                                         I        source hclk source_cg                                      	  Wdisabled          usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            [    )             )>              	  =mac ippc            G                     W   =                 .      /                          $     '                     '         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         \   2      h         s        Wokay               3      usb@112a0000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            [    *             *>              	  =mac ippc            G                     W   >                 0      1                                '                  '         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         \   2      i         s        Wokay               3      usb@112b0000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            [    +             +>              	  =mac ippc            G                     W   ?                 2      3                                '                  '   	      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         \   2      j         s        Wokay               3      spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor          [    2                G      9                     o   '      '           spi sf axi                       +          	  Wdisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse             [                                  +      usb3-tx-imp@184,1            [             w                   I      usb3-rx-imp@184,2            [             w                  H      usb3-intr@185            [             w                  G      usb3-tx-imp@186,1            [             w                   F      usb3-rx-imp@186,2            [             w                  E      usb3-intr@187            [             w                  D      usb2-intr-p0@188,1           [             w             usb2-intr-p1@188,2           [             w            usb2-intr-p2@189,1           [             w            usb2-intr-p3@189,2           [             w               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                Wokay       usb-phy@0            [                             ref         |               >         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                Wokay       usb-phy@0            [                             ref         |               ?         i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                 "               G                                    @          ;      	  main dma                         +          	  Wdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                "                G                                    @         ;      	  main dma                         +            Wokay                      ;   A        -default    pmic@34           mediatek,mt6360          [   4                       e           IRQB       charger           mediatek,mt6360-chg          @   usb-otg-vbus-regulator          usb-otg-vbus            3usb-otg-vbus            B C(        Z X            4         regulator             mediatek,mt6360-regulator              B   buck1           BUCK1           3mt6360,buck1            B         Z                                   buck2           BUCK2           3mt6360,buck2            B         Z                                         B      ldo1            LDO1            3mt6360,ldo1         B O        Z 6                     ldo2            LDO2            3mt6360,ldo2         B O        Z 6                     ldo3            LDO3            3mt6360,ldo3         B O        Z 6                           <      ldo5            LDO5            3mt6360,ldo5         B )2        Z 6                           ;      ldo6            LDO6            3mt6360,ldo6         B          Z                        ldo7            LDO7            3mt6360,ldo7         B          Z                                          i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                 "               G                                    @         ;      	  main dma                         +          	  Wdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s           [    0                               @      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                 "                G                                    C          ;      	  main dma                         +          	  Wdisabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                "                G                                    C         ;      	  main dma                         +          	  Wdisabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                 "               G                                    C         ;      	  main dma                         +          	  Wdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [    0            "               G                                    C         ;      	  main dma                         +          	  Wdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [    @            "                G                                    C         ;      	  main dma                         +          	  Wdisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w           [    P                               C      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   *           Wokay       usb-phy@0            [                                ref da_ref          |               =      usb-phy@700          [                                  ref da_ref             D   E   F        intr rx_imp tx_imp          |            t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                Wokay       usb-phy@0            [                                ref da_ref          |               0      usb-phy@700          [                                  ref da_ref             G   H   I        intr rx_imp tx_imp          |               1         ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy            [                                 
  unipro mp           |          	  Wdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg           [                             clock-controller@14000000             mediatek,mt8195-vppsys0          [                                           smi@14010000              mediatek,mt8195-smi-sub-common           [                                               apb smi gals0              J           *               K      smi@14011000              mediatek,mt8195-smi-sub-common           [                                              apb smi gals0              J           *               g      smi@14012000              mediatek,mt8195-smi-common-vpp           [                                                      apb smi gals0 gals1            *               J      larb@14013000             mediatek,mt8195-smi-larb             [    0                              K                            apb smi            *               N      iommu@14018000            mediatek,mt8195-iommu-vpp            [                  8     L   M   N   O   P   Q   R   S   T   U   V   W   X   Y        G      R                             bclk                          *         clock-controller@14e00000             mediatek,mt8195-wpesys           [                                          clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0          [                              clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1          [    0                         larb@14e04000             mediatek,mt8195-smi-larb             [    @                              Z                            apb smi            *               m      larb@14e05000             mediatek,mt8195-smi-larb             [    P                              J                                  apb smi gals               *               P      clock-controller@14f00000             mediatek,mt8195-vppsys1          [                                          larb@14f02000             mediatek,mt8195-smi-larb             [                                   Z                                  apb smi gals               *               l      larb@14f03000             mediatek,mt8195-smi-larb             [    0                              K                                  apb smi gals               *               O      clock-controller@15000000             mediatek,mt8195-imgsys           [                                     $      larb@15001000             mediatek,mt8195-smi-larb             [                        	           [           $       $       $   
        apb smi gals               *               n      smi@15002000              mediatek,mt8195-smi-sub-common           [                         $      $                 apb smi gals0              J           *               ^      smi@15003000              mediatek,mt8195-smi-sub-common           [     0                   $       $       $   
        apb smi gals0              Z           *               [      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top          [                                    \      larb@15120000             mediatek,mt8195-smi-larb             [                        
           [           $      \            apb smi            *               o      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr           [                              clock-controller@15220000             mediatek,mt8195-imgsys1_wpe          [    "                                ]      larb@15230000             mediatek,mt8195-smi-larb             [    #                               [           $      ]            apb smi            *               p      clock-controller@15330000             mediatek,mt8195-ipesys           [    3                                %      larb@15340000             mediatek,mt8195-smi-larb             [    4                               ^           %      %           apb smi            *               Q      clock-controller@16000000             mediatek,mt8195-camsys           [                                     &      larb@16001000             mediatek,mt8195-smi-larb             [                                   _           &       &       &           apb smi gals               *               q      larb@16002000             mediatek,mt8195-smi-larb             [                                    `           &      &           apb smi            *               R      smi@16004000              mediatek,mt8195-smi-sub-common           [     @                   &       &       &           apb smi gals0              Z           *               _      smi@16005000              mediatek,mt8195-smi-sub-common           [     P                   &      &                 apb smi gals0              J           *               `      larb@16012000             mediatek,mt8195-smi-larb             [                                   `           a       a            apb smi            *                S      larb@16013000             mediatek,mt8195-smi-larb             [    0                              _           b       b            apb smi            *                r      larb@16014000             mediatek,mt8195-smi-larb             [    @                              `           c       c            apb smi            *   !            Y      larb@16015000             mediatek,mt8195-smi-larb             [    P                              _           d       d            apb smi            *   !            w      clock-controller@1604f000             mediatek,mt8195-camsys_rawa          [                                   a      clock-controller@1606f000             mediatek,mt8195-camsys_yuva          [                                   b      clock-controller@1608f000             mediatek,mt8195-camsys_rawb          [                                   c      clock-controller@160af000             mediatek,mt8195-camsys_yuvb          [    
                               d      clock-controller@16140000             mediatek,mt8195-camsys_mraw          [                                    e      larb@16141000             mediatek,mt8195-smi-larb             [                                  _           &       e       &           apb smi gals               *   "            v      larb@16142000             mediatek,mt8195-smi-larb             [                                   `           e       e            apb smi            *   "            X      clock-controller@17200000             mediatek,mt8195-ccusys           [                                     f      larb@17201000             mediatek,mt8195-smi-larb             [                                   `           f       f            apb smi            *               T      larb@1800d000             mediatek,mt8195-smi-larb             [                                   Z                                apb smi            *               u      larb@1800e000             mediatek,mt8195-smi-larb             [                                   g                              apb smi            *               W      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc          [                                           larb@1802e000             mediatek,mt8195-smi-larb             [                                  Z                              apb smi            *               t      clock-controller@1802f000             mediatek,mt8195-vdecsys          [                                         larb@1803e000             mediatek,mt8195-smi-larb             [                                  g                 !            apb smi            *               V      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1            [                                   !      clock-controller@190f3000             mediatek,mt8195-apusys_pll           [    0                         clock-controller@1a000000             mediatek,mt8195-vencsys          [                                     "      larb@1a010000             mediatek,mt8195-smi-larb             [                                   Z           "      "           apb smi            *               s      clock-controller@1b000000             mediatek,mt8195-vencsys_core1            [                                           syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon             [                       h                                    larb@1b010000             mediatek,mt8195-smi-larb             [                                   J                                   apb smi gals               *               U      ovl@1c000000          2    mediatek,mt8195-disp-ovl mediatek,mt8183-disp-ovl            [                      G      |                  *                             i           &   h                rdma@1c002000             mediatek,mt8195-disp-rdma            [                      G      ~                  *                            i            &   h                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color            [     0                G                        *                         &   h     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr            [     @                G                        *                         &   h     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal            [     P                G                        *                         &   h     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma            [     `                G                        *                         &   h     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither          [     p                G                        *                 	        &   h     p          dsc@1c009000              mediatek,mt8195-disp-dsc             [                     G                        *                         &   h               merge@1c014000            mediatek,mt8195-disp-merge           [    @                G                        *                         &   h     @          mutex@1c016000            mediatek,mt8195-disp-mutex           [    `                G                        *                         >  U      larb@1c018000             mediatek,mt8195-smi-larb             [                                   Z              (      (              apb smi gals               *               j      larb@1c019000             mediatek,mt8195-smi-larb             [                                  J              (                     apb smi gals               *               L      syscon@1c100000           mediatek,mt8195-vdosys1 syscon           [                                    #      smi@1c01b000              mediatek,mt8195-smi-common-vdo           [                           %      &      )      $        apb smi gals0 gals1            *               Z      iommu@1c01f000            mediatek,mt8195-iommu-vdo            [                  8     j   k   l   m   n   o   p   q   r   s   t   u   v   w        G                                      '        bclk               *               i      larb@1c102000             mediatek,mt8195-smi-larb             [                                   Z           #       #       #           apb smi gals               *               k      larb@1c103000             mediatek,mt8195-smi-larb             [    0                              J           #      #                  apb smi gals               *               M         chosen          Rserial0:921600n8          firmware       optee             linaro,optee-tz          fsmc          gpio-keys         
    gpio-keys           -default         ;   x   key-0           E      j         
  ^volume_up           d   s         s        o            memory@40000000          Omemory           [    @                reserved-memory                      +               optee@43200000                    [    C                memory@50000000           shared-dma-pool          [    P                        memory@53000000           shared-dma-pool          [    S       @        memory@54600000                   [    T`                memory@60000000           shared-dma-pool          [    `                        memory@62000000           shared-dma-pool          [    b       @              	compatible interrupt-parent #address-cells #size-cells model gce0 gce1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux input-enable bias-pull-up drive-strength bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 #io-channel-cells phys mediatek,syscon-wakeup wakeup-source vusb33-supply vbus-supply pinctrl-1 bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 bits #phy-cells interrupt-names richtek,vinovp-microvolt regulator-compatible LDO_VIN3-supply nvmem-cells nvmem-cell-names mediatek,smi mediatek,larb-id mediatek,larbs iommus mediatek,gce-client-reg mediatek,gce-events stdout-path label linux,code debounce-interval no-map 