     8     (              x                             $    mediatek,mt8183-evb mediatek,mt8183                                  +         !   7MediaTek MT8183 evaluation board       aliases          =/soc/i2c@11007000            B/soc/i2c@11011000            G/soc/i2c@11009000            L/soc/i2c@1100f000            Q/soc/i2c@11008000            V/soc/i2c@11016000            [/soc/i2c@11005000            `/soc/i2c@1101a000            e/soc/i2c@1101b000            j/soc/i2c@11014000            o/soc/i2c@11015000            u/soc/i2c@11017000            {/soc/ovl@14008000            /soc/ovl@14009000            /soc/ovl@1400a000            /soc/rdma@1400b000           /soc/rdma@1400c000           /soc/serial@11002000          opp-table-cluster0            operating-points-v2                           opp0-793000000               /D8@          	                  opp0-910000000               6=          
}                  opp0-1014000000              <pi          
                  opp0-1131000000              Ci                            opp0-1248000000              Jb           5                   opp0-1326000000              O	'          ~>                  opp0-1417000000              Tu@          P                  opp0-1508000000              YA           A            	      opp0-1586000000              ^p          6            
      opp0-1625000000              `ۈ@          
                  opp0-1677000000              c@          5                  opp0-1716000000              fH           f                  opp0-1781000000              j'@                            opp0-1846000000              n          B@                  opp0-1924000000              r                             opp0-1989000000              v@                               opp-table-cluster1            operating-points-v2                       #   opp1-793000000               /D8@          
`                  opp1-910000000               6=                            opp1-1014000000              <pi          q                  opp1-1131000000              Ci          X                  opp1-1248000000              Jb           5                   opp1-1326000000              O	'                            opp1-1417000000              Tu@          P                  opp1-1508000000              YA           Y            	      opp1-1586000000              ^p                      
      opp1-1625000000              `ۈ@          t                  opp1-1677000000              c@          5                  opp1-1716000000              fH           ~                  opp1-1781000000              j'@                            opp1-1846000000              n          B@                  opp1-1924000000              r                             opp1-1989000000              v@                               opp-table-cci             operating-points-v2                          opp-273000000                E@          	                  opp-338000000                %x          
}                  opp-403000000                J          
                  opp-463000000                                            opp-546000000                 L          5                   opp-624000000                %1|           ~>                  opp-689000000                )N@          P                  opp-767000000                -}          A            	      opp-845000000                2]@          6            
      opp-871000000                3g          
                  opp-923000000                7          5                  opp-962000000                9V          f                  opp-1027000000               =6                            opp-1092000000               A           B@                  opp-1144000000               D0                             opp-1196000000               GI                                cci           mediatek,mt8183-cci                               cci intermediate                                       !      cpus                         +       cpu-map    cluster0       core0                    core1                    core2                    core3                       cluster1       core0                    core1                    core2                    core3                          cpu@0           cpu           arm,cortex-a53                      !psci            /          B                                     cpu intermediate                         R   T        l           {   !                             cpu@1           cpu           arm,cortex-a53                     !psci            /          B                                     cpu intermediate                         R   T        l           {   !                             cpu@2           cpu           arm,cortex-a53                     !psci            /          B                                     cpu intermediate                         R   T        l           {   !                             cpu@3           cpu           arm,cortex-a53                     !psci            /          B                                     cpu intermediate                         R   T        l           {   !                             cpu@100         cpu           arm,cortex-a73                     !psci            /           B      "                              cpu intermediate                #        R           l           {   !           $                  cpu@101         cpu           arm,cortex-a73                    !psci            /           B      "                              cpu intermediate                #        R           l           {   !           $                  cpu@102         cpu           arm,cortex-a73                    !psci            /           B      "                              cpu intermediate                #        R           l           {   !           $                  cpu@103         cpu           arm,cortex-a73                    !psci            /           B      "                              cpu intermediate                #        R           l           {   !           $                  idle-states         psci       cpu-sleep             arm,idle-state                                                                        cluster-sleep-0           arm,idle-state                                                                     cluster-sleep-1           arm,idle-state                                                               "            opp-table-0           operating-points-v2                       ]   opp-300000000                           	h P      opp-320000000                           	 P      opp-340000000                C           	< P      opp-360000000                u*           	Ҧ P      opp-380000000                W           	 P      opp-400000000                ׄ           
z P      opp-420000000                           
 P      opp-460000000                k           
L P      opp-500000000                e           
} P      opp-540000000                 /           
` P      opp-580000000                "           
4 P      opp-620000000                $s            P      opp-653000000                &@          YF P      opp-698000000                )           A      opp-743000000                ,IG           6      opp-800000000                /            H         pmu-a53           arm,cortex-a53-pmu              %                    &      pmu-a73           arm,cortex-a73-pmu              %                    '      psci              arm,psci-1.0            (smc       fixed-factor-clock-13m            fixed-factor-clock                          (                              clk13m              2      oscillator            fixed-clock                     /        clk26m              (      timer             arm,armv8-timer             %      @                                               
             soc                      +             simple-bus           ?   efuse@8000000         %    mediatek,mt8183-efuse mediatek,efuse                                               +         	  Fdisabled          interrupt-controller@c000000              arm,gic-v3          M               %         ^      P                                  @              A             B                        	                   %   ppi-partitions     interrupt-partition-0           s                        &      interrupt-partition-1           s                        '            syscon@c530000            mediatek,mt8183-mcucfg syscon               S                                      interrupt-controller@c530a80          .    mediatek,mt8183-sysirq mediatek,mt6577-sysirq            ^        M               %            S
       P                  cpu-debug@d410000         &    arm,coresight-cpu-debug arm,primecell               A                     )   .      	   apb_pclk                     cpu-debug@d510000         &    arm,coresight-cpu-debug arm,primecell               Q                     )   .      	   apb_pclk                     cpu-debug@d610000         &    arm,coresight-cpu-debug arm,primecell               a                     )   .      	   apb_pclk                     cpu-debug@d710000         &    arm,coresight-cpu-debug arm,primecell               q                     )   .      	   apb_pclk                     cpu-debug@d810000         &    arm,coresight-cpu-debug arm,primecell                                    )   .      	   apb_pclk                     cpu-debug@d910000         &    arm,coresight-cpu-debug arm,primecell                                    )   .      	   apb_pclk                     cpu-debug@da10000         &    arm,coresight-cpu-debug arm,primecell                                    )   .      	   apb_pclk                     cpu-debug@db10000         &    arm,coresight-cpu-debug arm,primecell                                    )   .      	   apb_pclk                     syscon@10000000            mediatek,mt8183-topckgen syscon                                                    syscon@10001000            mediatek,mt8183-infracfg syscon                                         |               )      syscon@10003000           mediatek,mt8183-pericfg syscon               0                               P      pinctrl@10005000              mediatek,mt8183-pinctrl              P                                                                                                                                   D  iocfg0 iocfg1 iocfg2 iocfg3 iocfg4 iocfg5 iocfg6 iocfg7 iocfg8 eint                                *                    ^                          M               *   i2c0                :   pins_i2c              R  S                                i2c1                H   pins_i2c              Q  T                                i2c2                <   pins_i2c              g  h                                i2c3                F   pins_i2c              2  3                                i2c4                ;   pins_i2c              i  j                                i2c5                K   pins_i2c              0  1                                spi0                =   pins_spi              U  V  W  X                  mmc0default             S   pins_cmd_dat          $    {    }    ~        z                         pins_clk              |               pins_rst                                mmc0                T   pins_cmd_dat          $    {    }    ~        z                  )   
           e      pins_clk              |        )   
           f      pins_ds                   )   
           f      pins_rst                      )   
                  mmc1default             W   pins_cmd_dat                   "  !                           pins_clk                                       pins_pmu                           8         mmc1                X   pins_cmd_dat                   "  !          )                        e      pins_clk                      )              f                   spi1                G   pins_spi                                      spi2                I   pins_spi                     ^                  spi3                J   pins_spi                                      spi4                L   pins_spi                                      spi5                M   pins_spi                                      pwm1                E   pins_pwm              Z            syscon@10006000       )    mediatek,mt8183-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8183-power-controller                         +            D               D   power-domain@0                                )   /   )   7         audio audio1 audio2         D          power-domain@1                     X   )        D          power-domain@2                                     mfg                      +            D      power-domain@3                                  +            D           j   +   power-domain@4                     D          power-domain@5                     D          power-domain@6                     X   )        D                power-domain@7                   X            ,       ,      ,      ,      ,      ,      ,      ,      ,      ,   	      5   mm mm-0 mm-1 mm-2 mm-3 mm-4 mm-5 mm-6 mm-7 mm-8 mm-9            X   )        x   -                     +            D      power-domain@8                   @            .       .   	   .      .      .      .      .         .   cam cam-0 cam-1 cam-2 cam-3 cam-4 cam-5 cam-6           X   )        x   -        D          power-domain@9             	               "   /   	   /            isp isp-0 isp-1         X   )        x   -        D          power-domain@10            
        x   -        D          power-domain@11                    x   -        D          power-domain@12                  @         &      #   0       0      0      0      0      0         -   vpu vpu1 vpu-0 vpu-1 vpu-2 vpu-3 vpu-4 vpu-5            X   )        x   -                     +            D      power-domain@13                           $         vpu2            X   )        D          power-domain@14                           %         vpu3            X   )        D                      watchdog@10007000             mediatek,mt8183-wdt              p                |               Q      syscon@1000c000       "    mediatek,mt8183-apmixedsys syscon                                               A      pwrap@1000d000            mediatek,mt8183-pwrap                                pwrap                                    )   )         	   spi wrap       mt6358            mediatek,mt6358          ^            *                      M      mt6358codec           mediatek,mt6358-sound                     mt6358regulator           mediatek,mt6358-regulator      buck_vdram1         vdram1                     L          0                                          buck_vcore          vcore                                j                                         buck_vpa            vpa                    7          P                                buck_vproc11            vproc11                              j                                               $      buck_vproc12            vproc12                              j                                                     buck_vgpu           vgpu                                 j                                      +      buck_vs2            vs2                    L          0                           buck_vmodem         vmodem                               j                                        buck_vs1            vs1          B@         '{l          0                           ldo_vdram2          vdram2           	'         w@                ldo_vsim1           vsim1                     /M`                ldo_vibr            vibr             O         2Z           <      ldo_vrf12             regulator-fixed         vrf12            O         O           x      ldo_vio18             regulator-fixed         vio18            w@         w@          
                     V      ldo_vusb            vusb             -         /M`                         ldo_vcamio            regulator-fixed         vcamio           w@         w@          E      ldo_vcamd           vcamd                     w@          E      ldo_vcn18             regulator-fixed         vcn18            w@         w@                ldo_vfe28             regulator-fixed         vfe28            *         *                ldo_vsram_proc11            vsram_proc11                                 j                          ldo_vcn28             regulator-fixed         vcn28            *         *                ldo_vsram_others            vsram_others                                 j                          ldo_vsram_gpu         
  vsram_gpu                                j                       ^      ldo_vxo22             regulator-fixed         vxo22            !         !           x               ldo_vefuse          vefuse                                    ldo_vaux18            regulator-fixed         vaux18           w@         w@                ldo_vmch            vmch             ,@          2Z           <            Y      ldo_vbif28            regulator-fixed         vbif28           *         *                ldo_vsram_proc12            vsram_proc12                                 j                          ldo_vcama1          vcama1           w@         -          E      ldo_vemc            vemc             ,@          2Z           <            U      ldo_vio28             regulator-fixed         vio28            *         *                ldo_va12              regulator-fixed         va12             O         O                         ldo_vrf18             regulator-fixed         vrf18            w@         w@           x      ldo_vcn33_bt          	  vcn33_bt             2Z         5g                ldo_vcn33_wifi          vcn33_wifi           2Z         5g                ldo_vcama2          vcama2           w@         -          E      ldo_vmc         vmc          w@         2Z           <            Z      ldo_vldo28          vldo28           *         -                ldo_vaud28            regulator-fixed         vaud28           *         *                ldo_vsim2           vsim2                     /M`                   mt6358rtc             mediatek,mt6358-rtc       mt6358keys            mediatek,mt6358-keys       power           4   t         C      home            4   f               keyboard@10010000             mediatek,mt6779-keypad                                                     (         kpd       	  Fdisabled          scp@10500000              mediatek,mt8183-scp              P             \             	  sram cfg                                  )            main            Q   1      	  Fdisabled          timer@10017000        ,    mediatek,mt8183-timer mediatek,mt6765-timer             p                                      2      iommu@10205000            mediatek,mt8183-m4u              P                                  _   3   4   5   6   7   8   9        n               `      mailbox@10238000              mediatek,mt8183-gce             #       @                           {               )            gce             _      auxadc@11001000       .    mediatek,mt8183-auxadc mediatek,mt8173-auxadc                                    )   #         main                       Fokay                @      serial@11002000       *    mediatek,mt8183-uart mediatek,mt6577-uart                                        [               (   )         	   baud bus            Fokay          serial@11003000       *    mediatek,mt8183-uart mediatek,mt6577-uart                0                       \               (   )         	   baud bus          	  Fdisabled          serial@11004000       *    mediatek,mt8183-uart mediatek,mt6577-uart                @                       ]               (   )         	   baud bus          	  Fdisabled          i2c@11005000              mediatek,mt8183-i2c               P                                    W               )   W   )   *      	   main dma                                    +          	  Fdisabled          i2c@11007000              mediatek,mt8183-i2c               p                                    Q               )   
   )   *      	   main dma                                    +            Fokay            default            :        /       i2c@11008000              mediatek,mt8183-i2c                                                   R               )      )   *   )   G         main dma arb                                    +            Fokay            default            ;        / B@      i2c@11009000              mediatek,mt8183-i2c                                                  S               )      )   *   )   I         main dma arb                                    +            Fokay            default            <        /       spi@1100a000              mediatek,mt8183-spi                      +                                        x                  6         )            parent-clk sel-clk spi-clk          Fokay            default            =                  svs@1100b000              mediatek,mt8183-svs                                                    )   	         main               >   ?      (  svs-calibration-data t-calibration-data       thermal@1100b000                         mediatek,mt8183-thermal                                  )   	   )   #         therm auxadc               )                   L              @           A           ?        calibration-data                B      thermal-zones      cpu-thermal         #   d        9          G   B            W     trips      trip-point0         i 	        u          passive       trip-point1         i 8        u          passive             C      cpu-crit            i 8        u        	  critical             cooling-maps       map0               C      0                               map1               C      0                                     tzts1           #            9            G   B           W     trips         cooling-maps             tzts2           #            9            G   B           W     trips         cooling-maps             tzts3           #            9            G   B           W     trips         cooling-maps             tzts4           #            9            G   B           W     trips         cooling-maps             tzts5           #            9            G   B           W     trips         cooling-maps             tztsABB         #            9            G   B           W     trips         cooling-maps                pwm@1100e000              mediatek,mt8183-disp-pwm                                                      D                                )   5         main mm       pwm@11006000              mediatek,mt8183-pwm              `                         0      )      )      )      )      )      )            top main pwm1 pwm2 pwm3 pwm4            Fokay               E        default       i2c@1100f000              mediatek,mt8183-i2c                                                   T               )      )   *      	   main dma                                    +            Fokay            default            F        /       spi@11010000              mediatek,mt8183-spi                      +                                        |                  6         )   8         parent-clk sel-clk spi-clk          Fokay            default            G                  i2c@11011000              mediatek,mt8183-i2c                                                 U               )   9   )   *      	   main dma                                    +            Fokay            default            H        /       spi@11012000              mediatek,mt8183-spi                      +                                                          6         )   ;         parent-clk sel-clk spi-clk          Fokay            default            I                  spi@11013000              mediatek,mt8183-spi                      +                0                                         6         )   <         parent-clk sel-clk spi-clk          Fokay            default            J                  i2c@11014000              mediatek,mt8183-i2c              @                                                  )   H   )   *   )   G         main dma arb                                    +          	  Fdisabled          i2c@11015000              mediatek,mt8183-i2c              P                                                   )   J   )   *   )   I         main dma arb                                    +          	  Fdisabled          i2c@11016000              mediatek,mt8183-i2c              `                                    V               )   D   )   *   )   E         main dma arb                                    +            Fokay            default            K        / B@      i2c@11017000              mediatek,mt8183-i2c              p                                                  )   F   )   *   )   E         main dma arb                                    +          	  Fdisabled          spi@11018000              mediatek,mt8183-spi                      +                                                         6         )   K         parent-clk sel-clk spi-clk          Fokay            default            L                  spi@11019000              mediatek,mt8183-spi                      +                                                         6         )   L         parent-clk sel-clk spi-clk          Fokay            default            M                  i2c@1101a000              mediatek,mt8183-i2c                                                 X               )   b   )   *      	   main dma                                    +          	  Fdisabled          i2c@1101b000              mediatek,mt8183-i2c                                                  Y               )   c   )   *      	   main dma                                    +          	  Fdisabled          usb@11201000          #    mediatek,mt8183-mtu3 mediatek,mtu3                       .      >              	  mac ippc                   H              N      O               )   =   )   Z         sys_ck ref_ck              P      e                     +            ?      	  Fdisabled       usb@11200000          '    mediatek,mt8183-xhci mediatek,mtk-xhci                                mac                I               )   =   )   Z         sys_ck ref_ck         	  Fdisabled             audio-controller@11220000              mediatek,mt8183-audiosys syscon             "                                R   mt8183-afe-pcm            mediatek,mt8183-audio                                Q         	  audiosys               D         D      R      R      R      R      R      R      R      R      R      R      R      R   
   R   	   R      R       )   /   )   7                  0            H            L            K            O      t      u      v      w      x      y      z      {      |      }      ~         (     w   aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adc_adda6_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_i2s1_bclk_sw aud_i2s2_bclk_sw aud_i2s3_bclk_sw aud_i2s4_bclk_sw aud_tdm_clk aud_tml_clk aud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_aud_intbus top_syspll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_clk26m_clk           mmc@11230000              mediatek,mt8183-mmc              #                                     M                     )      )            source hclk source_cg           Fokay            default state_uhs              S           T                                               %         4         E         M        S (        b   U        n   V        {                    U               mmc@11240000              mediatek,mt8183-mmc              $                                     N                  	   )      )   (         source hclk source_cg           Fokay            default state_uhs              W           X                                                                          M        b   Y        n   Z                  C               dsi-phy@11e50000              mediatek,mt8183-mipi-tx                                  A                                   mipi_tx0_pll               [        calibration-data                a      efuse@11f10000        %    mediatek,mt8183-efuse mediatek,efuse                                              +      calib@180                            ?      calib@190                            [      calib@580                d            >         t-phy@11f40000        .    mediatek,mt8183-tphy mediatek,generic-tphy-v2                        +           ?                     Fokay       usb-phy@0                              (         ref                               Fokay                N      usb-phy@700              	             (         ref                    Fokay                O         syscon@13000000           mediatek,mt8183-mfgcfg syscon                                                \      gpu@13040000          &    mediatek,mt8183-mali arm,mali-bifrost                       @       $                                     !job mmu gpu             \               D      D      D           1core0 core1 core2               ]        D   +        P   ^      syscon@14000000           mediatek,mt8183-mmsys syscon                                             |           \   _          _              c   _                      ,      mdp3-rdma0@14001000           mediatek,mt8183-mdp3-rdma                                c   _                 {                 D               ,      ,              `            \   _              _                 mdp3-rsz0@14003000            mediatek,mt8183-mdp3-rsz                 0                c   _     0            {                  ,         mdp3-rsz1@14004000            mediatek,mt8183-mdp3-rsz                 @                c   _     @            {                  ,         mdp3-wrot0@14005000           mediatek,mt8183-mdp3-wrot                P                c   _     P            {      !           D               ,              `         mdp3-wdma@14006000            mediatek,mt8183-mdp3-wdma                `                c   _     `            {      "           D               ,   )           `         ovl@14008000              mediatek,mt8183-disp-ovl                                                      D               ,              `            c   _               ovl@14009000              mediatek,mt8183-disp-ovl-2l                                                   D               ,              `           c   _               ovl@1400a000              mediatek,mt8183-disp-ovl-2l                                                   D               ,              `           c   _               rdma@1400b000             mediatek,mt8183-disp-rdma                                                     D               ,              `                      c   _               rdma@1400c000             mediatek,mt8183-disp-rdma                                                     D               ,              `                      c   _               color@1400e000        6    mediatek,mt8183-disp-color mediatek,mt8173-disp-color                                                     D               ,           c   _               ccorr@1400f000            mediatek,mt8183-disp-ccorr                                                    D               ,           c   _               aal@14010000              mediatek,mt8183-disp-aal                                                      D               ,           c   _                gamma@14011000            mediatek,mt8183-disp-gamma                                                   D               ,           c   _               dither@14012000           mediatek,mt8183-disp-dither                                                   D               ,           c   _                dsi@14014000              mediatek,mt8183-dsi             @                                     D               ,      ,       a         engine digital hs              ,              a        dphy          mutex@14016000            mediatek,mt8183-disp-mutex              `                                     D           {              c   _     `          larb@14017000             mediatek,mt8183-smi-larb                p                x   -            ,      ,              D            apb smi             3      smi@14019000              mediatek,mt8183-smi-common                                   ,       ,       ,      ,            apb smi gals0 gals1            D               -      mdp3-ccorr@1401c000           mediatek,mt8183-mdp3-ccorr                              c   _                 {      1            ,   +      syscon@15020000           mediatek,mt8183-imgsys syscon                                               /      larb@15021000             mediatek,mt8183-smi-larb                                x   -            /   	   /   	   ,            apb smi gals               D   	            8      larb@1502f000             mediatek,mt8183-smi-larb                                x   -            /      /      ,   	         apb smi gals               D   	            5      syscon@16000000           mediatek,mt8183-vdecsys syscon                                               b      larb@16010000             mediatek,mt8183-smi-larb                                 x   -            b       b            apb smi            D   
            4      syscon@17000000           mediatek,mt8183-vencsys syscon                                               c      larb@17010000             mediatek,mt8183-smi-larb                                 x   -            c       c             apb smi            D               7      venc_jpg@17030000         +    mediatek,mt8183-jpgenc mediatek,mtk-jpgenc                                                    `      `              D               c            jpgenc        syscon@19000000            mediatek,mt8183-ipu_conn syscon                                              0      syscon@19010000           mediatek,mt8183-ipu_adl syscon                                        syscon@19180000       !    mediatek,mt8183-ipu_core0 syscon                                          syscon@19280000       !    mediatek,mt8183-ipu_core1 syscon                (                          syscon@1a000000           mediatek,mt8183-camsys syscon                                                .      larb@1a001000             mediatek,mt8183-smi-larb                                 x   -            .       .       ,            apb smi gals               D               9      larb@1a002000             mediatek,mt8183-smi-larb                                  x   -            .   	   .   	   ,            apb smi gals               D               6         memory@40000000         memory              @                chosen          serial0:921600n8          reserved-memory                      +            ?   scp_mem_region            shared-dma-pool             P                              1         ntc@0             murata,ncp03wf104            w@         p                       @             	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 i2c7 i2c8 i2c9 i2c10 i2c11 ovl0 ovl-2l0 ovl-2l1 rdma0 rdma1 serial0 opp-shared phandle opp-hz opp-microvolt required-opps clocks clock-names operating-points-v2 proc-supply cpu device_type reg enable-method capacity-dmips-mhz cpu-idle-states dynamic-power-coefficient #cooling-cells mediatek,cci entry-method local-timer-stop arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us interrupts #clock-cells clock-div clock-mult clock-output-names clock-frequency ranges status #interrupt-cells interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux mediatek,pull-up-adv mediatek,drive-strength-adv bias-disable input-enable bias-pull-up bias-pull-down drive-strength output-high #power-domain-cells mediatek,infracfg domain-supply mediatek,smi mediatek,dmic-mode regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-always-on regulator-allowed-modes linux,keycodes wakeup-source memory-region mediatek,larbs #iommu-cells #mbox-cells #io-channel-cells pinctrl-names pinctrl-0 mediatek,pad-select nvmem-cells nvmem-cell-names #thermal-sensor-cells resets mediatek,auxadc mediatek,apmixedsys polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution power-domains #pwm-cells phys mediatek,syscon-wakeup reset-names pinctrl-1 bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply assigned-clocks assigned-clock-parents non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 cap-sdio-irq no-mmc keep-power-in-suspend #phy-cells mediatek,discth interrupt-names power-domain-names mali-supply sram-supply mboxes mediatek,gce-client-reg mediatek,gce-events iommus mediatek,rdma-fifo-size phy-names stdout-path no-map pullup-uv pullup-ohm pulldown-ohm io-channels 