  G   8  Ѩ   (              p                             1    google,tomato-rev2 google,tomato mediatek,mt8195                                     +            7Acer Tomato (rev2) board       aliases          =/soc/mailbox@10320000            B/soc/mailbox@10330000            G/soc/i2c@11e00000            L/soc/i2c@11e01000            Q/soc/i2c@11e02000            V/soc/i2c@11e03000            [/soc/i2c@11e04000            `/soc/i2c@11d00000            e/soc/i2c@11d02000            j/soc/mmc@11230000            o/soc/mmc@11240000            t/soc/serial@11001100          cpus                         +       cpu@0            |cpu           arm,cortex-a55                        psci                             ec3@           4                                                  	      cpu@100          |cpu           arm,cortex-a55                       psci                             ec3@           4                                                  
      cpu@200          |cpu           arm,cortex-a55                       psci                             ec3@           4                                                        cpu@300          |cpu           arm,cortex-a55                       psci                             ec3@           4                                                        cpu@400          |cpu           arm,cortex-a78                       psci                            f                                                                    cpu@500          |cpu           arm,cortex-a78                       psci                            f                                                                    cpu@600          |cpu           arm,cortex-a78                       psci                            f                                                                    cpu@700          |cpu           arm,cortex-a78                       psci                            f                                                                    cpu-map    cluster0       core0           	   	      core1           	   
      core2           	         core3           	         core4           	         core5           	         core6           	         core7           	               idle-states         psci       cpu-off-l             arm,idle-state                     1        B   2        S   _        c  D                 cpu-off-b             arm,idle-state                     1        B   -        S           c                   cluster-off-l             arm,idle-state                    1        B   7        S           c  H                 cluster-off-b             arm,idle-state                    1        B   2        S           c                      l2-cache0             cache                                l2-cache1             cache                                l3-cache              cache                       dsu-pmu           arm,dsu-pmu         t                          	   
                        dmic-codec            dmic-codec                        2      mt8195-sound                     	  disabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             '      oscillator-26m            fixed-clock                              clk26m                   oscillator-32k            fixed-clock                                 clk32k        performance-controller@11bc10             mediatek,cpufreq-hw                            0                                   pmu-a55           arm,cortex-a55-pmu                      t                  pmu-a78           arm,cortex-a78-pmu                      t                  psci              arm,psci-1.0             smc       timer             arm,armv8-timer                   @  t                                             
             soc                      +             simple-bus              interrupt-controller@c000000              arm,gic-v3                     (                        ?                                              t      	                     ppi-partitions     interrupt-partition-0           T   	   
                       interrupt-partition-1           T                                   syscon@10000000            mediatek,mt8195-topckgen syscon                                                    syscon@10001000       .    mediatek,mt8195-infracfg_ao syscon simple-mfd                                            ]                    syscon@10003000           mediatek,mt8195-pericfg syscon                0                              3      pinctrl@10005000              mediatek,mt8195-pinctrl               P                                                                                                         B  jiocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            t                                          ?        t                                          default                 >  I2S_SPKR_MCLK I2S_SPKR_DATAIN I2S_SPKR_LRCK I2S_SPKR_BCLK EC_AP_INT_ODL AP_FLASH_WP_L TCHPAD_INT_ODL EDP_HPD_1V8 AP_I2C_CAM_SDA AP_I2C_CAM_SCL AP_I2C_TCHPAD_SDA_1V8 AP_I2C_TCHPAD_SCL_1V8 AP_I2C_AUD_SDA AP_I2C_AUD_SCL AP_I2C_TPM_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 EC_AP_HPD_OD  PCIE_NVME_RST_L PCIE_NVME_CLKREQ_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL PCIE_WAKE_1V8_ODL CLK_24M_CAM0 CAM1_SEN_EN AP_I2C_PWR_SCL_1V8 AP_I2C_PWR_SDA_1V8 AP_I2C_MISC_SCL AP_I2C_MISC_SDA EN_PP5000_HDMI_X AP_HDMITX_HTPLG  AP_HDMITX_SCL_1V8 AP_HDMITX_SDA_1V8 AP_RTC_CLK32K AP_EC_WATCHDOG_L SRCLKENA0 SRCLKENA1 PWRAP_SPI0_CS_L PWRAP_SPI0_CK PWRAP_SPI0_MOSI PWRAP_SPI0_MISO SPMI_SCL SPMI_SDA    I2S_HP_DATAIN I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAOUT SD_CD_ODL EN_PP3300_DISP_X TCHSCR_RST_1V8_L TCHSCR_REPORT_DISABLE EN_PP3300_WLAN_X BT_KILL_1V8_L I2S_SPKR_DATAOUT WIFI_KILL_1V8_L BEEP_ON SCP_I2C_SENSOR_SCL_1V8 SCP_I2C_SENSOR_SDA_1V8     AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 SCP_VREQ_VAO AP_SPI_GSC_TPM_CLK AP_SPI_GSC_TPM_MOSI AP_SPI_GSC_TPM_CS_L AP_SPI_GSC_TPM_MISO EN_PP1000_CAM_X AP_EDP_BKLTEN  USB3_HUB_RST_L  WLAN_ALERT_ODL EC_IN_RW_ODL GSC_AP_INT_ODL HP_INT_ODL CAM0_RST_L CAM1_RST_L TCHSCR_INT_1V8_L CAM1_DET_L RST_ALC1011_L   BL_PWM_1V8 UART_AP_TX_DBG_RX UART_DBG_TX_AP_RX EN_SPKR AP_EC_WARM_RST_REQ UART_SCP_TX_DBGCON_RX UART_DBGCON_TX_SCP_RX   KPCOL0  MT6315_GPU_INT MT6315_PROC_BC_INT SD_CMD SD_CLK SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RSTB EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL   MT6360_INT_ODL SCP_JTAG0_TRSTN AP_SPI_EC_CS_L AP_SPI_EC_CLK AP_SPI_EC_MOSI AP_SPI_EC_MISO SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TDO SCP_JTAG0_TDI AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO                 cr50-irq-default-pins              M   pins-gsc-ap-int-odl           X                   cros-ec-irq-default-pins               0   pins-ec-ap-int-odl                        e                  i2c0-default-pins              G   pins-bus                	         	                   i2c1-default-pins              H   pins-bus              
                               i2c2-default-pins              K   pins-bus                         	                   i2c3-default-pins              L   pins-bus                                             i2c4-default-pins              N   pins-bus                                  .            i2c5-default-pins              C   pins-bus                         	                   i2c7-default-pins              D   pins-bus                         	         mmc0-default-pins              6   pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                 .              e      pins-clk              z        .           =   f      pins-rst              x        .              e         mmc0-uhs-pins              7   pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                 .              e      pins-clk              z        .           =   f      pins-ds                   .           =   f      pins-rst              x        .              e         mmc1-detect-pins               ;   pins-insert           6                   mmc1-default-pins              :   pins-cmd-dat              n  p  q  r  s                 .              e      pins-clk              o        .           =   f         nor-default-pins               A   pins-ck-io                        .            =      pins-cs                   .                     pio-default-pins                  pins-wifi-enable              :          L        .         pins-low-power-pd         ,          .   /   0   A   B   C   D                         =      pins-low-power-pupd       <    M   N   O   P   S   U   Z   [   ]   ^   _   `   h   i   k                  =   e      pins-low-power-hdmi-disable                  !   "   #                   =      pins-low-power-pcie0-disable                                       =         scp-default-pins               )   pins-vreq             L         	                  spi0-default-pins              /   pins-cs-mosi-clk                           	      pins-miso                      =         subpmic-default-pins               E   pins-subpmic-int-n                                        trackpad-default-pins              I   pins-int-n                                        touchscreen-default-pins               O   pins-int-n            \                     e      pins-rst              8          L      pins-report-sw            9          X            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8195-power-controller                         +            c              +   power-domain@8                                   +            c      power-domain@9              	                      wmfg                                 +            c      power-domain@10             
        c          power-domain@11                     c          power-domain@12                     c          power-domain@13                     c          power-domain@14                     c                power-domain@15                                             	      @      A      K                                                                                                                                wvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +            c      power-domain@24                                    wvdec1-0                    c          power-domain@27                                c          power-domain@16                   8              $      %      &      '      (      )      D  wvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +            c      power-domain@17                                               wvppsys1 vppsys1-0 vppsys1-1                    c          power-domain@22                                                    $  wwepsys-0 wepsys-1 wepsys-2 wepsys-3                    c          power-domain@23                                     wvdec0-0                    c          power-domain@25                        !            wvdec2-0                    c          power-domain@26                                c          power-domain@18                               "       "      "         &  wvdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +            c      power-domain@19                                c          power-domain@20                                c          power-domain@21                           Q        whdmi_tx         c             power-domain@28                        #       #   
        wimg-0 img-1                                 +            c      power-domain@29                     c          power-domain@30                              #      $           wipe ipe-0 ipe-1                    c             power-domain@31                   (     %       %      %      %      %           wcam-0 cam-1 cam-2 cam-3 cam-4                                   +            c      power-domain@32                      c          power-domain@33             !        c          power-domain@34             "        c                   power-domain@0                                  c          power-domain@1                                 c          power-domain@2                      c          power-domain@3                      c          power-domain@4                            5      7        wcsi_rx_top csi_rx_top1          c          power-domain@5                         &           wether           c          power-domain@6                            X      n        wadsp adsp1                       +                       c      power-domain@7                             g      "      n      2        waudio audio1 audio2 audio3                     c                   watchdog@10007000             mediatek,mt8195-wdt                        p                ]              .      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                                                     timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer              p                t      	                  '      pwrap@10024000            mediatek,mt8195-pwrap syscon                 @                jpwrap           t                                         	  wspi wrap                  $                 pmic              mediatek,mt6359          ?                               mt6359codec       regulators     buck_vs1            vs1          5          !        '             C      buck_vgpu11         vgpu11                    7        W          '           l                   C      buck_vmodem         vmodem                            W  *        '         buck_vpu            vpu                   7        W          '           l                   C      buck_vcore          vcore                              W          '           l                   C      buck_vs2            vs2          5          j         '             C      buck_vpa            vpa                    7        '  ,      buck_vproc2         vproc2                    7        W  L        '           l                buck_vproc1         vproc1                    7        W  L        '           l                buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub             dp         dp         C      ldo_vaud18          vaud18           w@         w@        '         ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z      ldo_vrf12           vrf12                               C      ldo_vusb            vusb             -         -        '           C           4      ldo_vsram_proc2         vsram_proc2                            W  L        '            C      ldo_vio18           vio18                             '           C      ldo_vcamio          vcamio                          ldo_vcn18           vcn18            w@         w@        '         ldo_vfe28           vfe28            *         *        '   x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@        '            C      ldo_vsram_others            vsram_others             q         q        W          '            C      ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !         C      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *        '         ldo_vio28           vio28            *         2Z         C      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z           8      ldo_vcn33_2_bt          vcn33_2_bt           *         5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   C      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               W  *        '         ldo_vufs            vufs                               C           9      ldo_vm18            vm18                               C      ldo_vbbck           vbbck                     O      ldo_vsram_proc1         vsram_proc1                            W  L        '            C      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              mt6359rtc             mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi                  p                            jpmif spmimst                               E      (  wpmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                                   +       mt6315@6              mediatek,mt6315-regulator                      regulators     vbuck1          vbuck1          Vbcpu                     7        '           W  j        l                   C            mt6315@7              mediatek,mt6315-regulator                      regulators     vbuck1          vbuck1          Vgpu             	h         7        '           W  j        l                   C               infra-iommu@10315000              mediatek,mt8195-iommu-infra              1P       P       P  t                                                                                  mailbox@10320000              mediatek,mt8195-gce              2        @         t                                                  u      mailbox@10330000              mediatek,mt8195-gce              3        @         t                                             scp@10500000              mediatek,mt8195-scp       0       P             r             p                 jsram cfg l1tcm          t                     okay            mediatek/mt8195/scp.img            (        default            )   cros-ec-rpmsg             google,cros-ec-rpmsg            cros-ec-rpmsg            clock-controller@10720000             mediatek,mt8195-scp_adsp                 r                               *      dsp@10803000              mediatek,mt8195-dsp               0                           	  jcfg sram          ,        X         n         *          #      K  wadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             +           rx tx              ,   -      	  disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox                            `                t                        ,      mailbox@10817000              mediatek,mt8195-adsp-mbox                            p                t                        -      mt8195-afe-pcm@10890000           mediatek,mt8195-audio                                               +           t      6                  .         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   *            wclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  disabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 t                                     	  wbaud bus            okay          serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 t                                     	  wbaud bus          	  disabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 t                                     	  wbaud bus          	  disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 t                                    	  wbaud bus          	  disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 t                                    	  wbaud bus          	  disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 t                                    	  wbaud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                                wmain            '         	  disabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                 0                              &      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  t                                                wparent-clk sel-clk spi-clk          okay            default            /        9       ec@0                         +              google,cros-ec-spi                                        default            0        M -   keyboard-backlight            google,cros-kbd-led-backlight         i2c-tunnel            google,cros-ec-i2c-tunnel           _                         +       sbs-battery@b             sbs,sbs-battery                     q                       regulator@0           google,cros-ec-regulator                         mt_pmic_vmc_ldo          O         6           =      regulator@1           google,cros-ec-regulator                        mt_pmic_vmch_ldo             )2         6           <      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector                      dual            host            source        connector@1           usb-c-connector                     dual            host            source           keyboard-controller           google,cros-ec-keyb                                     D     t x c  	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (                 	  	                 spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  t                                        3        wparent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  t                                        4        wparent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                 0                t                                        5        wparent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 t                                        <        wparent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 t                                        =        wparent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave                                t                            R        wspi                                   	  disabled          spi@1101e000              mediatek,mt8195-spi-slave                                t                            S        wspi                                   	  disabled          usb@11200000          '    mediatek,mt8195-xhci mediatek,mtk-xhci                               >              	  jmac ippc            t                         1      2                 ,      -                          $        /                     B      $  wsys_ck ref_ck mcu_ck dma_ck xhci_ck         "   3      g         9        okay            G   4        U   5      mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               #                              t                                                wsource hclk source_cg           okay            a            k         }         L        Q                                                      default state_uhs              6           7           8           9      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               $                              t                                        $        wsource hclk source_cg                                       okay            a                          6           Q                           default state_uhs              :   ;           :                  (           <           =      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               %                              t                                         I        wsource hclk source_cg                                      	  disabled          usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci                )             )>              	  jmac ippc            t                        >                 .      /                          $     &                     &         $  wsys_ck ref_ck mcu_ck dma_ck xhci_ck         "   3      h         9        okay            G   4        U   5      usb@112a0000          '    mediatek,mt8195-xhci mediatek,mtk-xhci                *             *>              	  jmac ippc            t                        ?                 0      1                                &                  &         $  wsys_ck ref_ck mcu_ck dma_ck xhci_ck         "   3      i         9        okay            G   4        U   5      usb@112b0000          '    mediatek,mt8195-xhci mediatek,mtk-xhci                +             +>              	  jmac ippc            t                        @                 2      3                                &                  &   	      $  wsys_ck ref_ck mcu_ck dma_ck xhci_ck         "   3      j         9        okay             6        G   4        U   5      spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor              2                t      9                     o   &      &           wspi sf axi                       +            okay            default            A   flash@0           jedec,spi-nor                        Mu         G           X            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                                               +      usb3-tx-imp@184,1                         i                  U      usb3-rx-imp@184,2                         i                 T      usb3-intr@185                         i                 S      usb3-tx-imp@186,1                         i                  R      usb3-rx-imp@186,2                         i                 Q      usb3-intr@187                         i                 P      usb2-intr-p0@188,1                        i             usb2-intr-p1@188,2                        i            usb2-intr-p2@189,1                        i            usb2-intr-p3@189,2                        i               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0                                         wref         n              ?         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0                                         wref         n              @         i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               t                                    B          ;      	  wmain dma                         +            okay                      default            C      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                t                                    B         ;      	  wmain dma                         +          	  disabled          i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               t                                    B         ;      	  wmain dma                         +            okay                      default            D   pmic@34                      mediatek,mt6360             4         ?                         yIRQB            default            E         9         clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s               0                              B      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "                t                                    F          ;      	  wmain dma                         +            okay                      default            G      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                t                                    F         ;      	  wmain dma                         +            okay                        0        default            H   trackpad@15           elan,ekth3000                                        default            I           J         9         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               t                                    F         ;      	  wmain dma                         +            okay                      default            K      i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c               0            "               t                                    F         ;      	  wmain dma                         +            okay                      default            L   tpm@50            google,cr50             P              X           default            M         i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c               @            "                t                                    F         ;      	  wmain dma                         +            okay                      default            N   touchscreen@10            hid-over-i2c                                         \           default            O           
           J        okay             clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w               P                              F      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   +           okay       usb-phy@0                                            wref da_ref          n              >      usb-phy@700                                            wref da_ref             P   Q   R        intr rx_imp tx_imp          n            t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0                                            wref da_ref          n              1      usb-phy@700                                            wref da_ref             S   T   U        intr rx_imp tx_imp          n              2         ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy                                             
  wunipro mp           n          	  disabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg                                        clock-controller@14000000             mediatek,mt8195-vppsys0                                                    smi@14010000              mediatek,mt8195-smi-sub-common                                                          wapb smi gals0              V           +              W      smi@14011000              mediatek,mt8195-smi-sub-common                                                         wapb smi gals0              V           +              s      smi@14012000              mediatek,mt8195-smi-common-vpp                                                                 wapb smi gals0 gals1            +              V      larb@14013000             mediatek,mt8195-smi-larb                 0                	              W                            wapb smi            +              Z      iommu@14018000            mediatek,mt8195-iommu-vpp                              8     X   Y   Z   [   \   ]   ^   _   `   a   b   c   d   e        t      R                             wbclk                          +         clock-controller@14e00000             mediatek,mt8195-wpesys                                                    clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0                                        clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1              0                         larb@14e04000             mediatek,mt8195-smi-larb                 @                	              f                            wapb smi            +              {      larb@14e05000             mediatek,mt8195-smi-larb                 P                	              V                                  wapb smi gals               +              \      clock-controller@14f00000             mediatek,mt8195-vppsys1                                                   larb@14f02000             mediatek,mt8195-smi-larb                                  	              f                                  wapb smi gals               +              z      larb@14f03000             mediatek,mt8195-smi-larb                 0                	              W                                  wapb smi gals               +              [      clock-controller@15000000             mediatek,mt8195-imgsys                                               #      larb@15001000             mediatek,mt8195-smi-larb                                  	   	           g           #       #       #   
        wapb smi gals               +              |      smi@15002000              mediatek,mt8195-smi-sub-common                                    #      #                 wapb smi gals0              V           +              j      smi@15003000              mediatek,mt8195-smi-sub-common                0                   #       #       #   
        wapb smi gals0              f           +              g      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                                             h      larb@15120000             mediatek,mt8195-smi-larb                                  	   
           g           #      h            wapb smi            +              }      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                                         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe              "                               i      larb@15230000             mediatek,mt8195-smi-larb                 #                 	              g           #      i            wapb smi            +              ~      clock-controller@15330000             mediatek,mt8195-ipesys               3                               $      larb@15340000             mediatek,mt8195-smi-larb                 4                 	              j           $      $           wapb smi            +              ]      clock-controller@16000000             mediatek,mt8195-camsys                                               %      larb@16001000             mediatek,mt8195-smi-larb                                  	              k           %       %       %           wapb smi gals               +                    larb@16002000             mediatek,mt8195-smi-larb                                   	              l           %      %           wapb smi            +              ^      smi@16004000              mediatek,mt8195-smi-sub-common                @                   %       %       %           wapb smi gals0              f           +              k      smi@16005000              mediatek,mt8195-smi-sub-common                P                   %      %                 wapb smi gals0              V           +              l      larb@16012000             mediatek,mt8195-smi-larb                                  	              l           m       m            wapb smi            +               _      larb@16013000             mediatek,mt8195-smi-larb                 0                	              k           n       n            wapb smi            +                     larb@16014000             mediatek,mt8195-smi-larb                 @                	              l           o       o            wapb smi            +   !           e      larb@16015000             mediatek,mt8195-smi-larb                 P                	              k           p       p            wapb smi            +   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa                                            m      clock-controller@1606f000             mediatek,mt8195-camsys_yuva                                            n      clock-controller@1608f000             mediatek,mt8195-camsys_rawb                                            o      clock-controller@160af000             mediatek,mt8195-camsys_yuvb              
                              p      clock-controller@16140000             mediatek,mt8195-camsys_mraw                                             q      larb@16141000             mediatek,mt8195-smi-larb                                 	              k           %       q       %           wapb smi gals               +   "                 larb@16142000             mediatek,mt8195-smi-larb                                  	              l           q       q            wapb smi            +   "           d      clock-controller@17200000             mediatek,mt8195-ccusys                                               r      larb@17201000             mediatek,mt8195-smi-larb                                  	              l           r       r            wapb smi            +              `      larb@1800d000             mediatek,mt8195-smi-larb                                  	              f                                wapb smi            +                    larb@1800e000             mediatek,mt8195-smi-larb                                  	              s                              wapb smi            +              c      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc                                                    larb@1802e000             mediatek,mt8195-smi-larb                                 	              f                              wapb smi            +                    clock-controller@1802f000             mediatek,mt8195-vdecsys                                                  larb@1803e000             mediatek,mt8195-smi-larb                                 	              s                 !            wapb smi            +              b      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1                                              !      clock-controller@190f3000             mediatek,mt8195-apusys_pll               0                         clock-controller@1a000000             mediatek,mt8195-vencsys                                              t      larb@1a010000             mediatek,mt8195-smi-larb                                  	              f           t      t           wapb smi            +                    clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                                v      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                    u                                   larb@1b010000             mediatek,mt8195-smi-larb                                  	              V           v       v                  wapb smi gals               +              a      ovl@1c000000          2    mediatek,mt8195-disp-ovl mediatek,mt8183-disp-ovl                                  t      |                  +                          )   w           0   u                rdma@1c002000             mediatek,mt8195-disp-rdma                                  t      ~                  +                         )   w            0   u                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                 0                t                        +                         0   u     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                 @                t                        +                         0   u     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                 P                t                        +                         0   u     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                 `                t                        +                         0   u     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither               p                t                        +                 	        0   u     p          dsc@1c009000              mediatek,mt8195-disp-dsc                                  t                        +                         0   u               merge@1c014000            mediatek,mt8195-disp-merge               @                t                        +                         0   u     @          mutex@1c016000            mediatek,mt8195-disp-mutex               `                t                        +                         H  U      larb@1c018000             mediatek,mt8195-smi-larb                                 	               f              (      (              wapb smi gals               +              x      larb@1c019000             mediatek,mt8195-smi-larb                                 	              V              (                     wapb smi gals               +              X      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                                              "      smi@1c01b000              mediatek,mt8195-smi-common-vdo                                      %      &      )      $        wapb smi gals0 gals1            +              f      iommu@1c01f000            mediatek,mt8195-iommu-vdo                              8     x   y   z   {   |   }   ~                             t                                      '        wbclk               +              w      larb@1c102000             mediatek,mt8195-smi-larb                                  	              f           "       "       "           wapb smi gals               +              y      larb@1c103000             mediatek,mt8195-smi-larb                 0                	              V           "      "                  wapb smi gals               +              Y         chosen          \serial0:115200n8          memory@40000000          |memory               @                regulator-pp3300-ldo-z5           regulator-fixed         pp3300_ldo_z5            C         h         2Z         2Z        z         regulator-pp3300-s3           regulator-fixed       
  pp3300_s3            C         h         2Z         2Z        z              J      regulator-pp3300-z2           regulator-fixed       
  pp3300_z2            C         h         2Z         2Z        z                    regulator-pp4200-z2           regulator-fixed       
  pp4200_z2            C         h         @@         @@        z         regulator-pp5000-s5           regulator-fixed       
  pp5000_s5            C         h         LK@         LK@        z         regulator-ppvar-sys           regulator-fixed       
  ppvar_sys            C         h                 regulator-5v0-usb-vbus            regulator-fixed       	  usb-vbus             LK@         LK@                  C           5      reserved-memory                      +               memory@50000000           shared-dma-pool              P                             (            	compatible interrupt-parent #address-cells #size-cells model gce0 gce1 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c7 mmc0 mmc1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts cpus num-channels wakeup-delay-ms mediatek,platform status #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit pinctrl-names pinctrl-0 gpio-line-names pinmux input-enable bias-pull-up bias-disable drive-strength-microamp drive-strength bias-pull-down output-high output-low #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-compatible #iommu-cells #mbox-cells firmware-name memory-region mediatek,rpmsg-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names #io-channel-cells mediatek,pad-select spi-max-frequency google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap phys mediatek,syscon-wakeup wakeup-source vusb33-supply vbus-supply bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable pinctrl-1 vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 usb2-lpm-disable spi-rx-bus-width spi-tx-bus-width bits #phy-cells interrupt-names i2c-scl-internal-delay-ns vcc-supply hid-descr-addr post-power-on-delay-ms vdd-supply nvmem-cells nvmem-cell-names mediatek,smi mediatek,larb-id mediatek,larbs iommus mediatek,gce-client-reg mediatek,gce-events stdout-path regulator-boot-on vin-supply enable-active-high no-map 