     8     (                                           $    mediatek,mt8192-evb mediatek,mt8192                                  +         !   7MediaTek MT8192 evaluation board       aliases          =/soc/ovl@14005000            B/soc/ovl@14006000            J/soc/ovl@14014000            R/soc/rdma@14007000           X/soc/rdma@14015000           ^/soc/serial@11002000          fixed-factor-clock-13m            fixed-factor-clock           f             s            z                        clk13m              $      oscillator0           fixed-clock          f                      clk26m                    oscillator1           fixed-clock          f                         clk32k        cpus                         +       cpu@0            cpu           arm,cortex-a55                        psci             ec3@                                                                 
      cpu@100          cpu           arm,cortex-a55                       psci             ec3@                                                                       cpu@200          cpu           arm,cortex-a55                       psci             ec3@                                                                       cpu@300          cpu           arm,cortex-a55                       psci             ec3@                                                                       cpu@400          cpu           arm,cortex-a76                       psci             f                           	                                            cpu@500          cpu           arm,cortex-a76                       psci             f                           	                                            cpu@600          cpu           arm,cortex-a76                       psci             f                           	                                            cpu@700          cpu           arm,cortex-a76                       psci             f                           	                                            cpu-map    cluster0       core0               
      core1                     core2                     core3                     core4                     core5                     core6                     core7                           l2-cache0             cache                                 l2-cache1             cache                           	      l3-cache              cache                     idle-states         $psci       cpu-sleep-l           arm,idle-state          1           H        Y   7        j           z                    cpu-sleep-b           arm,idle-state          1           H        Y   #        j           z                    cluster-sleep-l           arm,idle-state          1          H        Y   <        j           z  \                  cluster-sleep-b           arm,idle-state          1          H        Y   (        j           z                          pmu-a55           arm,cortex-a55-pmu                                        pmu-a76           arm,cortex-a76-pmu                                        psci              arm,psci-1.0             smc       timer             arm,armv8-timer                   @                                               
                 ]@      soc                      +             simple-bus              performance-controller@11bc10             mediatek,cpufreq-hw                            0                                    interrupt-controller@c000000              arm,gic-v3                                                                                                 	                      ppi-partitions     interrupt-partition-0              
                           interrupt-partition-1                                               syscon@10000000            mediatek,mt8192-topckgen syscon                                 f                     syscon@10001000            mediatek,mt8192-infracfg syscon                                f                                syscon@10003000           mediatek,mt8192-pericfg syscon                0                 f               (      pinctrl@10005000              mediatek,mt8192-pinctrl               P                                                                                                                                                ]  
iocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint                     $           0                                                                          syscon@10006000       )    mediatek,mt8192-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8192-power-controller                         +            <               *   power-domain@0                        s            :      /        Paudio audio1 audio2         \           <          power-domain@1                       s              Pconn            \           <          power-domain@2                       s              Pmfg                      +            <      power-domain@3                      \                        +            <      power-domain@4                      <          power-domain@5                      <          power-domain@6                      <          power-domain@7                      <          power-domain@8                      <                power-domain@9              	      (   s                                    !  Pdisp disp-0 disp-1 disp-2 disp-3            \                        +            <      power-domain@10             
      (   s                                       Pipe ipe-0 ipe-1 ipe-2 ipe-3         \           <          power-domain@11                      s                           Pisp isp-0 isp-1         \           <          power-domain@12                      s                           Pisp2 isp2-0 isp2-1          \           <          power-domain@13                      s                  
  Pmdp mdp-0           \           <          power-domain@14                      s      3              Pvenc venc-0         \           <          power-domain@15                       s      4                           Pvdec vdec-0 vdec-1 vdec-2           \                        +            <      power-domain@16                      s                           Pvdec2-0 vdec2-1 vdec2-2         <             power-domain@17                   (   s      
                                     Pcam cam-0 cam-1 cam-2 cam-3         \                        +            <      power-domain@18                      s   !            Pcam_rawa-0          <          power-domain@19                      s   "            Pcam_rawb-0          <          power-domain@20                      s   #            Pcam_rawc-0          <                      watchdog@10007000             mediatek,mt8192-wdt               p                               )      syscon@1000c000       "    mediatek,mt8192-apmixedsys syscon                                  f               '      timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer              p                                       s   $      pwrap@10026000            mediatek,mt6873-pwrap                `                
pwrap                                  s                   	  Pspi wrap            n              ~         pmic              mediatek,mt6359                        mt6359codec       regulators     buck_vs1            vs1          5          !                           buck_vgpu11         vgpu11                    7                                             buck_vmodem         vmodem                              *                 buck_vpu            vpu                   7                                             buck_vcore          vcore                                                                   buck_vs2            vs2          5          j                            buck_vpa            vpa                    7          ,      buck_vproc2         vproc2                    7          L                                   buck_vproc1         vproc1                    7          L                                   buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@                 ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z      ldo_vrf12           vrf12                            ldo_vusb            vusb             -         -                         ldo_vsram_proc2         vsram_proc2                              L                          ldo_vio18           vio18                                              ldo_vcamio          vcamio                          ldo_vcn18           vcn18            w@         w@                 ldo_vfe28           vfe28            *         *           x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@                          ldo_vsram_others            vsram_others                                                  ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !               ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *                 ldo_vio28           vio28            *         2Z               ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z      ldo_vcn33_2_bt          vcn33_2_bt           *         5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                         ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                                 *                 ldo_vufs            vufs                            ldo_vm18            vm18                                     ldo_vbbck           vbbck                     O      ldo_vsram_proc1         vsram_proc1                              L                          ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              mt6359rtc             mediatek,mt6358-rtc             spmi@10027000             mediatek,mt6873-spmi                  p                            
pmif spmimst             s                   8      (  Ppmif_sys_ck pmif_tmr_ck spmimst_clk_mux         n              ~            mailbox@10228000              mediatek,mt8192-gce              "       @                               1            s              Pgce             3      clock-controller@10720000             mediatek,mt8192-scp_adsp                 r                  f           =fail          serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart                                         m                s               	  Pbaud bus            =okay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart                 0                       n                s               	  Pbaud bus          	  =disabled          clock-controller@11007000             mediatek,mt8192-imp_iic_wrap_c                p                 f         spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M                    Pparent-clk sel-clk spi-clk        	  =disabled          pwm@1100e000              mediatek,mt8183-disp-pwm                                                        D            s      !      8        Pmain mm       	  =disabled          spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M            <        Pparent-clk sel-clk spi-clk        	  =disabled          spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M            >        Pparent-clk sel-clk spi-clk        	  =disabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                 0                                       s      M            ?        Pparent-clk sel-clk spi-clk        	  =disabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            L        Pparent-clk sel-clk spi-clk        	  =disabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            M        Pparent-clk sel-clk spi-clk        	  =disabled          spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            m        Pparent-clk sel-clk spi-clk        	  =disabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            n        Pparent-clk sel-clk spi-clk        	  =disabled          scp@10500000              mediatek,mt8192-scp       0       P             r             p                 
sram cfg l1tcm                                s              Pmain          	  =disabled                F      usb@11200000          '    mediatek,mt8192-xhci mediatek,mtk-xhci                               >              	  
mac ippc            O          a               chost            s   %      &           n      "      #        ~      ]      ]          s      7   '               R      $  Psys_ck ref_ck mcu_ck dma_ck xhci_ck          x           (      f      	  =disabled          syscon@11210000           mediatek,mt8192-audsys syscon                !                   f               +   mt8192-afe-pcm            mediatek,mt8192-audio                                    )         	  audiosys               '        \                         *            s   +       +      +      +      +      +      +      +      +      +      +   	   +   
   +      +      +      +      +      +      +      +         /      :                  H      /      e      0      i      +      g      ,      k      ;      <      =      >      ?      @      A      B      C      D                                                                        7        u  Paud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adda6_adc_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_tdm_clk aud_tml_clk aud_nle aud_dac_hires_clk aud_adc_hires_clk aud_adc_hires_tml aud_adda6_adc_hires_clk aud_3rd_dac_clk aud_3rd_dac_predis_clk aud_3rd_dac_tml aud_3rd_dac_hires_clk aud_infra_clk aud_infra_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d4_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d4 top_mux_aud_eng2 top_apll2_d4 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_i2s6_m_sel top_i2s7_m_sel top_i2s8_m_sel top_i2s9_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_apll12_div5 top_apll12_div6 top_apll12_div7 top_apll12_div8 top_apll12_div9 top_mux_audio_h top_clk26m_clk             pcie@11230000             mediatek,mt8192-pcie             pci              #                	  
pcie-mac                         +         0   s      +      '      *      j      ^      \      /  Ppl_250m tl_26m tl_96m tl_32k peri_26m top_133m          n      )        ~      Q                                           8                                                                                        `                    ,                      ,                     ,                     ,      interrupt-controller                                                 ,         spi@11234000              mediatek,mt8192-nor              #@                                      s      :      w      ]        Pspi sf axi          n      :        ~                        +          	  =disabled          efuse@11c10000        %    mediatek,mt8192-efuse mediatek,efuse                                               +      data1@1c0                 X      calib@580                 h         i2c@11cb0000              mediatek,mt8192-i2c                            !s                       s                s   -          x      	  Pmain dma             z                        +          	  =disabled          clock-controller@11cb1000             mediatek,mt8192-imp_iic_wrap_e                                f               -      i2c@11d00000              mediatek,mt8192-i2c                            !v                      w                s   .          x      	  Pmain dma             z                        +          	  =disabled          i2c@11d01000              mediatek,mt8192-i2c                           !w                     x                s   .         x      	  Pmain dma             z                        +          	  =disabled          i2c@11d02000              mediatek,mt8192-i2c                            !y                      y                s   .         x      	  Pmain dma             z                        +          	  =disabled          clock-controller@11d03000             mediatek,mt8192-imp_iic_wrap_s               0                 f               .      i2c@11d20000              mediatek,mt8192-i2c                            !q                       q                s   /          x      	  Pmain dma             z                        +          	  =disabled          i2c@11d21000              mediatek,mt8192-i2c                           !q                     r                s   /         x      	  Pmain dma             z                        +          	  =disabled          i2c@11d22000              mediatek,mt8192-i2c                            !s                     t                s   /         x      	  Pmain dma             z                        +          	  =disabled          clock-controller@11d23000              mediatek,mt8192-imp_iic_wrap_ws              0                 f               /      i2c@11e00000              mediatek,mt8192-i2c                            !u                       u                s   0          x      	  Pmain dma             z                        +          	  =disabled          clock-controller@11e01000             mediatek,mt8192-imp_iic_wrap_w                                f               0      t-phy@11e40000        .    mediatek,mt8192-tphy mediatek,generic-tphy-v2                        +                           usb-phy@0                            s           Pref                        %      usb-phy@700               	          s           Pref                        &         dsi-phy@11e50000              mediatek,mt8183-mipi-tx                                s   '   
         f                         mipi_tx0_pll          	  =disabled                6      i2c@11f00000              mediatek,mt8192-i2c                            !p                      p                s   1          x      	  Pmain dma             z                        +          	  =disabled          i2c@11f01000              mediatek,mt8192-i2c                           !u                      v                s   1         x      	  Pmain dma             z                        +          	  =disabled          clock-controller@11f02000             mediatek,mt8192-imp_iic_wrap_n                                 f               1      clock-controller@11f10000             mediatek,mt8192-msdc_top                                   f               2      mmc@11f60000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                                    c             8   s         2   	   2      2      2      2      2         3  Psource hclk source_cg sys_cg pclk_cg axi_cg ahb_cg        	  =disabled          mmc@11f70000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                                    g             8   s         2   
   2      2      2      2      2         3  Psource hclk source_cg sys_cg pclk_cg axi_cg ahb_cg        	  =disabled          clock-controller@13fbf000             mediatek,mt8192-mfgcfg                                f         syscon@14000000           mediatek,mt8192-mmsys syscon                                    f                         3          3              !   3                            mutex@14001000            mediatek,mt8192-disp-mutex                                                       s               9               *   	      smi@14002000              mediatek,mt8192-smi-common                                   s                                Papb smi gals0 gals1            *   	            4      larb@14003000             mediatek,mt8192-smi-larb                  0                M            ^   4         s              Papb smi            *   	            7      larb@14004000             mediatek,mt8192-smi-larb                  @                M           ^   4         s              Papb smi            *   	            8      ovl@14005000              mediatek,mt8192-disp-ovl                  P                                       s              k   5      5              *   	        !   3     P          ovl@14006000              mediatek,mt8192-disp-ovl-2l               `                                         *   	         s              k   5   "   5            !   3     `          rdma@14007000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma               p                                       s              k   5           r              *   	        !   3     p          color@14009000        6    mediatek,mt8192-disp-color mediatek,mt8173-disp-color                                                         *   	         s              !   3               ccorr@1400a000            mediatek,mt8192-disp-ccorr                                                        *   	         s      	        !   3               aal@1400b000          2    mediatek,mt8192-disp-aal mediatek,mt8183-disp-aal                                                         *   	         s              !   3               gamma@1400c000        6    mediatek,mt8192-disp-gamma mediatek,mt8183-disp-gamma                                                         *   	         s              !   3               postmask@1400d000             mediatek,mt8192-disp-postmask                                                         *   	         s              !   3               dither@1400e000       8    mediatek,mt8192-disp-dither mediatek,mt8183-disp-dither                                                       *   	         s      
        !   3               dsi@14010000              mediatek,mt8183-dsi                                     	                s                6        Pengine digital hs           s   6        dphy               *   	                    	  =disabled       port       endpoint                ovl@14014000              mediatek,mt8192-disp-ovl-2l              @                                        *   	         s              k   5   #   5   !        !   3     @          rdma@14015000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma              P                                        *   	         s              k   5   %        r           !   3     P          dpi@14016000              mediatek,mt8192-dpi              `                                      s      !         '           Ppixel engine pll          	  =disabled          m4u@1401d000              mediatek,mt8192-m4u                            <     7   8   9   :   ;   <   =   >   ?   @   A   B   C   D   E                              s              Pbclk               *   	                       5      clock-controller@15020000             mediatek,mt8192-imgsys                                 f                     larb@1502e000             mediatek,mt8192-smi-larb                                 M   	        ^   4         s                      Papb smi            *               =      clock-controller@15820000             mediatek,mt8192-imgsys2                                f                     larb@1582e000             mediatek,mt8192-smi-larb                                 M           ^   4         s                      Papb smi            *               >      larb@1600d000             mediatek,mt8192-smi-larb                                  M           ^   4         s                      Papb smi            *               ;      clock-controller@1600f000             mediatek,mt8192-vdecsys_soc                                f                     larb@1602e000             mediatek,mt8192-smi-larb                                 M           ^   4         s                      Papb smi            *               :      clock-controller@1602f000             mediatek,mt8192-vdecsys                               f                     clock-controller@17000000             mediatek,mt8192-vencsys                                 f                     larb@17010000             mediatek,mt8192-smi-larb                                  M           ^   4         s                     Papb smi            *               <      vcodec@17020000           mediatek,mt8192-vcodec-enc                               X  k   5      5      5      5      5      5      5      5      5      5      5                 5                  F           *            s            
  Pvenc-set1           n      3        ~      W      clock-controller@1a000000             mediatek,mt8192-camsys                                  f                      larb@1a001000             mediatek,mt8192-smi-larb                                  M           ^   4         s                       Papb smi            *               ?      larb@1a002000             mediatek,mt8192-smi-larb                                   M           ^   4         s                      Papb smi            *               @      larb@1a00f000             mediatek,mt8192-smi-larb                                  M           ^   4         s   !      !            Papb smi            *               A      larb@1a010000             mediatek,mt8192-smi-larb                                  M           ^   4         s   "      "            Papb smi            *               B      larb@1a011000             mediatek,mt8192-smi-larb                                 M           ^   4         s   #       #           Papb smi            *               C      clock-controller@1a04f000             mediatek,mt8192-camsys_rawa                               f               !      clock-controller@1a06f000             mediatek,mt8192-camsys_rawb                               f               "      clock-controller@1a08f000             mediatek,mt8192-camsys_rawc                               f               #      clock-controller@1b000000             mediatek,mt8192-ipesys                                  f                     larb@1b00f000             mediatek,mt8192-smi-larb                                  M           ^   4         s                    Papb smi            *   
            E      larb@1b10f000             mediatek,mt8192-smi-larb                                 M           ^   4         s                     Papb smi            *   
            D      clock-controller@1f000000             mediatek,mt8192-mdpsys                                  f                     larb@1f002000             mediatek,mt8192-smi-larb                                   M           ^   4         s                    Papb smi            *               9         chosen          serial0:921600n8          memory@40000000          memory               @                   	compatible interrupt-parent #address-cells #size-cells model ovl0 ovl-2l0 ovl-2l2 rdma0 rdma4 serial0 #clock-cells clocks clock-div clock-mult clock-output-names phandle clock-frequency device_type reg enable-method cpu-idle-states next-level-cache performance-domains capacity-dmips-mhz cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges #power-domain-cells clock-names mediatek,infracfg assigned-clocks assigned-clock-parents regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #mbox-cells status #pwm-cells interrupts-extended interrupt-names phys wakeup-source mediatek,syscon-wakeup resets reset-names mediatek,apmixedsys mediatek,topckgen power-domains bus-range interrupt-map-mask interrupt-map #phy-cells mboxes mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus mediatek,rdma-fifo-size phy-names mediatek,larbs #iommu-cells mediatek,scp stdout-path 