  O   8     (              `                             $    mediatek,mt6795-evb mediatek,mt6795                                  +         !   7MediaTek MT6795 Evaluation Board       psci              arm,psci-0.2             =smc       cpus                         +       cpu@0            Dcpu           arm,cortex-a53           Ppsci             ^             b            s                     cpu@1            Dcpu           arm,cortex-a53           Ppsci             ^            b            s                     cpu@2            Dcpu           arm,cortex-a53           Ppsci             ^            b            s                     cpu@3            Dcpu           arm,cortex-a53           Ppsci             ^            b            s               	      cpu@100          Dcpu           arm,cortex-a53           Ppsci             ^            b            s               
      cpu@101          Dcpu           arm,cortex-a53           Ppsci             ^           b            s                     cpu@102          Dcpu           arm,cortex-a53           Ppsci             ^           b            s                     cpu@103          Dcpu           arm,cortex-a53           Ppsci             ^           b            s                     cpu-map    cluster0       core0                     core1                     core2                     core3               	         cluster1       core0               
      core1                     core2                     core3                           l2-cache0             cache                                 l2-cache1             cache                                    oscillator-26m            fixed-clock                                clk26m                    oscillator-32k            fixed-clock                         }          clk32k                    dummy13m              fixed-clock           ]@                               pmu           arm,cortex-a53-pmu        0                    	          
                                  	      timer             arm,armv8-timer                   0                                 
        soc                      +             simple-bus               pinctrl@10005000              mediatek,mt6795-pinctrl           ^     P                           
   base eint                                                                                    #        8                     watchdog@10007000             mediatek,mt6795-wdt          ^     p                                   I           V         timer@10008000        ,    mediatek,mt6795-timer mediatek,mt6577-timer          ^                                        b            intpol-controller@10200620        .    mediatek,mt6795-sysirq mediatek,mt6577-sysirq            #        8                        ^                                timer@10200670            mediatek,mt6795-systimer             ^     p                       @           b           iclk13m        interrupt-controller@10221000             arm,gic-400         8                        #      @   ^    "            "              "@             "`                        	                    cci@10390000              arm,cci-400                      +            ^    9                          9        slave-if@1000             arm,cci-400-ctrl-if       	  uace-lite             ^            slave-if@4000             arm,cci-400-ctrl-if         uace          ^  @                      slave-if@5000             arm,cci-400-ctrl-if         uace          ^  P                      pmu@9000              arm,cci-400-pmu,r1           ^     P       <          :          ;          <          =          >            serial@11002000       *    mediatek,mt6795-uart mediatek,mt6577-uart            ^                              [           b           okay          serial@11003000       *    mediatek,mt6795-uart mediatek,mt6577-uart            ^     0                        \           b         	  disabled          serial@11004000       *    mediatek,mt6795-uart mediatek,mt6577-uart            ^     @                        ]           b         	  disabled          serial@11005000       *    mediatek,mt6795-uart mediatek,mt6577-uart            ^     P                        ^           b         	  disabled             aliases         /soc/serial@11002000            /soc/serial@11003000            /soc/serial@11004000            /soc/serial@11005000          memory@40000000          Dmemory           ^    @               chosen          serial0:921600n8             	compatible interrupt-parent #address-cells #size-cells model method device_type enable-method reg cci-control-port next-level-cache phandle cpu cache-level #clock-cells clock-frequency clock-output-names interrupts interrupt-affinity ranges reg-names gpio-controller #gpio-cells gpio-ranges interrupt-controller #interrupt-cells #reset-cells timeout-sec clocks clock-names interface-type status serial0 serial1 serial2 serial3 stdout-path 