  P   8     (              |                             $    mediatek,mt8195-evb mediatek,mt8195                                  +         !   7MediaTek MT8195 evaluation board       aliases          =/soc/mailbox@10320000            B/soc/mailbox@10330000            G/soc/serial@11001100          cpus                         +       cpu@0            Ocpu           arm,cortex-a55           [             _psci             m                ec3@           4                                                   	      cpu@100          Ocpu           arm,cortex-a55           [            _psci             m                ec3@           4                                                   
      cpu@200          Ocpu           arm,cortex-a55           [            _psci             m                ec3@           4                                                         cpu@300          Ocpu           arm,cortex-a55           [            _psci             m                ec3@           4                                                         cpu@400          Ocpu           arm,cortex-a78           [            _psci             m               f                                                                     cpu@500          Ocpu           arm,cortex-a78           [            _psci             m               f                                                                     cpu@600          Ocpu           arm,cortex-a78           [            _psci             m               f                                                                     cpu@700          Ocpu           arm,cortex-a78           [            _psci             m               f                                                                     cpu-map    cluster0       core0               	      core1               
      core2                     core3                     core4                     core5                     core6                     core7                           idle-states          psci       cpu-off-l             arm,idle-state                                 2        &   _        6  D                  cpu-off-b             arm,idle-state                                 -        &           6                    cluster-off-l             arm,idle-state                                7        &           6  H                  cluster-off-b             arm,idle-state                                2        &           6                       l2-cache0             cache                                 l2-cache1             cache                                 l3-cache              cache                        dsu-pmu           arm,dsu-pmu         G                       R   	   
                        dmic-codec            dmic-codec          W           d   2      mt8195-sound            t         	  disabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m              &      oscillator-26m            fixed-clock                              clk26m                    oscillator-32k            fixed-clock                                 clk32k        performance-controller@11bc10             mediatek,cpufreq-hw           [                 0                                    pmu-a55           arm,cortex-a55-pmu                      G                  pmu-a78           arm,cortex-a78-pmu                      G                  psci              arm,psci-1.0             fsmc       timer             arm,armv8-timer                   @  G                                             
             soc                      +             simple-bus              interrupt-controller@c000000              arm,gic-v3                                                       [                                    G      	                      ppi-partitions     interrupt-partition-0           '   	   
                        interrupt-partition-1           '                                    syscon@10000000            mediatek,mt8195-topckgen syscon          [                                           syscon@10001000       .    mediatek,mt8195-infracfg_ao syscon simple-mfd            [                                0                     syscon@10003000           mediatek,mt8195-pericfg syscon           [     0                               /      pinctrl@10005000              mediatek,mt8195-pinctrl          [     P                                                                                                         B  =iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            G        W           c                               G                                        i2c0-pins               7   pins            o    	        v   e                                i2c1-pins               8   pins            o  
          v   e                                i2c4-pins               9   pins            o            v   e                    i2c6-pins               5   pins            o            v   e         i2c7-pins      pins            o            v   e         nor-pins                3   pins0           o                     pins1           o               v         uart0-pins              ,   pins            o  b  c            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd             [     `           power-controller          !    mediatek,mt8195-power-controller                         +                           (   power-domain@8           [                        +                  power-domain@9           [   	                      mfg                                 +                  power-domain@10          [   
                  power-domain@11          [                     power-domain@12          [                     power-domain@13          [                     power-domain@14          [                           power-domain@15          [                                   	      @      A      K                                                                                                                                vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +                  power-domain@24          [                          vdec1-0                              power-domain@27          [                                power-domain@16          [         8              $      %      &      '      (      )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +                  power-domain@17          [                                     vppsys1 vppsys1-0 vppsys1-1                              power-domain@22          [                                          $  wepsys-0 wepsys-1 wepsys-2 wepsys-3                              power-domain@23          [                          vdec0-0                              power-domain@25          [                           vdec2-0                              power-domain@26          [                                power-domain@18          [                     !       !      !         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +                  power-domain@19          [                                power-domain@20          [                                power-domain@21          [                 Q        hdmi_tx                      power-domain@28          [              "       "   
        img-0 img-1                                 +                  power-domain@29          [                     power-domain@30          [                    "      #           ipe ipe-0 ipe-1                                 power-domain@31          [         (     $       $      $      $      $           cam-0 cam-1 cam-2 cam-3 cam-4                                   +                  power-domain@32          [                      power-domain@33          [   !                  power-domain@34          [   "                           power-domain@0           [                                 power-domain@1           [                                power-domain@2           [                     power-domain@3           [                     power-domain@4           [                 5      7        csi_rx_top csi_rx_top1                    power-domain@5           [              %           ether                     power-domain@6           [                 X      n        adsp adsp1                       +                             power-domain@7           [                  g      "      n      2        audio audio1 audio2 audio3                                        watchdog@10007000             mediatek,mt8195-wdt                   [     p                0               +      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon            [                                          timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer          [    p                G      	                  &      pwrap@10024000            mediatek,mt8195-pwrap syscon             [    @                =pwrap           G                                         	  spi wrap                  $                    spmi@10027000             mediatek,mt8195-spmi              [    p                            =pmif spmimst                               E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                    infra-iommu@10315000              mediatek,mt8195-iommu-infra          [    1P       P       P  G                                                                         .         mailbox@10320000              mediatek,mt8195-gce          [    2        @         G                      ;                             _      mailbox@10330000              mediatek,mt8195-gce          [    3        @         G                      ;                       scp@10500000              mediatek,mt8195-scp       0   [    P             r             p                 =sram cfg l1tcm          G                   	  disabled          clock-controller@10720000             mediatek,mt8195-scp_adsp             [    r                                '      dsp@10803000              mediatek,mt8195-dsp           [    0                           	  =cfg sram          ,        X         n         '          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          G   (           Urx tx           `   )   *      	  disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           ;             [    `                G                         )      mailbox@10817000              mediatek,mt8195-adsp-mbox           ;             [    p                G                         *      mt8195-afe-pcm@10890000           mediatek,mt8195-audio            [                     g           G   (           G      6               y   +         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   '            clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  disabled                      serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                     	  baud bus            okay            default            ,      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                     	  baud bus          	  disabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                     	  baud bus          	  disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                    	  baud bus          	  disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                    	  baud bus          	  disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart            [                     G                                    	  baud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc            [                                    main                       okay          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon            [     0                               %      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                     G                                                parent-clk sel-clk spi-clk        	  disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                     G                                        3        parent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                     G                                        4        parent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [    0                G                                        5        parent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                    G                                        <        parent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             [                    G                                        =        parent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave            [                    G                            R        spi                                   	  disabled          spi@1101e000              mediatek,mt8195-spi-slave            [                    G                            S        spi                                   	  disabled          usb@11200000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            [                   >              	  =mac ippc            G                         -      .                 ,      -                          $        /                     B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck            /      g                 okay          mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           [    #                              G                                                source hclk source_cg         	  disabled          mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           [    $                              G                                        $        source hclk source_cg                                     	  disabled          mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           [    %                              G                                         I        source hclk source_cg                                      	  disabled          usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            [    )             )>              	  =mac ippc            G                        0                 .      /                          $     %                     %         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck            /      h                 okay          usb@112a0000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            [    *             *>              	  =mac ippc            G                        1                 0      1                                %                  %         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck            /      i                 okay          usb@112b0000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            [    +             +>              	  =mac ippc            G                        2                 2      3                                %                  %   	      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck            /      j                 okay                   spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor          [    2                G      9                     o   %      %           spi sf axi                       +            okay            default            3   flash@0           jedec,spi-nor            [                     efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse             [                                  +      usb3-tx-imp@184,1            [                                ?      usb3-rx-imp@184,2            [                               >      usb3-intr@185            [                               =      usb3-tx-imp@186,1            [                                <      usb3-rx-imp@186,2            [                               ;      usb3-intr@187            [                               :      usb2-intr-p0@188,1           [                          usb2-intr-p1@188,2           [                         usb2-intr-p2@189,1           [                         usb2-intr-p3@189,2           [                            t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0            [                             ref                        1         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0            [                             ref                        2         i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                 "               G                                    4          ;      	  main dma                         +          	  disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                "                G                                    4         ;      	  main dma                         +            okay            default            5                i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                 "               G                                    4         ;      	  main dma                         +          	  disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s           [    0                               4      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                 "                G                                    6          ;      	  main dma                         +            okay            default            7                i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                "                G                                    6         ;      	  main dma                         +            okay            default            8                i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [                 "               G                                    6         ;      	  main dma                         +          	  disabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [    0            "               G                                    6         ;      	  main dma                         +          	  disabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           [    @            "                G                                    6         ;      	  main dma                         +            okay            default            9                clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w           [    P                               6      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                G   (           okay       usb-phy@0            [                                ref da_ref                         0      usb-phy@700          [                                  ref da_ref             :   ;   <        intr rx_imp tx_imp                      t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0            [                                ref da_ref                         -      usb-phy@700          [                                  ref da_ref             =   >   ?        intr rx_imp tx_imp                         .         ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy            [                                 
  unipro mp                     	  disabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg           [                             clock-controller@14000000             mediatek,mt8195-vppsys0          [                                           smi@14010000              mediatek,mt8195-smi-sub-common           [                                               apb smi gals0           0   @        G   (               A      smi@14011000              mediatek,mt8195-smi-sub-common           [                                              apb smi gals0           0   @        G   (               ]      smi@14012000              mediatek,mt8195-smi-common-vpp           [                                                      apb smi gals0 gals1         G   (               @      larb@14013000             mediatek,mt8195-smi-larb             [    0                =           0   A                            apb smi         G   (               D      iommu@14018000            mediatek,mt8195-iommu-vpp            [                  8  N   B   C   D   E   F   G   H   I   J   K   L   M   N   O        G      R                             bclk            .           G   (         clock-controller@14e00000             mediatek,mt8195-wpesys           [                                          clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0          [                              clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1          [    0                         larb@14e04000             mediatek,mt8195-smi-larb             [    @                =           0   P                            apb smi         G   (               e      larb@14e05000             mediatek,mt8195-smi-larb             [    P                =           0   @                                  apb smi gals            G   (               F      clock-controller@14f00000             mediatek,mt8195-vppsys1          [                                          larb@14f02000             mediatek,mt8195-smi-larb             [                     =           0   P                                  apb smi gals            G   (               d      larb@14f03000             mediatek,mt8195-smi-larb             [    0                =           0   A                                  apb smi gals            G   (               E      clock-controller@15000000             mediatek,mt8195-imgsys           [                                     "      larb@15001000             mediatek,mt8195-smi-larb             [                     =   	        0   Q           "       "       "   
        apb smi gals            G   (               f      smi@15002000              mediatek,mt8195-smi-sub-common           [                         "      "                 apb smi gals0           0   @        G   (               T      smi@15003000              mediatek,mt8195-smi-sub-common           [     0                   "       "       "   
        apb smi gals0           0   P        G   (               Q      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top          [                                    R      larb@15120000             mediatek,mt8195-smi-larb             [                     =   
        0   Q           "      R            apb smi         G   (               g      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr           [                              clock-controller@15220000             mediatek,mt8195-imgsys1_wpe          [    "                                S      larb@15230000             mediatek,mt8195-smi-larb             [    #                 =           0   Q           "      S            apb smi         G   (               h      clock-controller@15330000             mediatek,mt8195-ipesys           [    3                                #      larb@15340000             mediatek,mt8195-smi-larb             [    4                 =           0   T           #      #           apb smi         G   (               G      clock-controller@16000000             mediatek,mt8195-camsys           [                                     $      larb@16001000             mediatek,mt8195-smi-larb             [                     =           0   U           $       $       $           apb smi gals            G   (               i      larb@16002000             mediatek,mt8195-smi-larb             [                      =           0   V           $      $           apb smi         G   (               H      smi@16004000              mediatek,mt8195-smi-sub-common           [     @                   $       $       $           apb smi gals0           0   P        G   (               U      smi@16005000              mediatek,mt8195-smi-sub-common           [     P                   $      $                 apb smi gals0           0   @        G   (               V      larb@16012000             mediatek,mt8195-smi-larb             [                     =           0   V           W       W            apb smi         G   (                I      larb@16013000             mediatek,mt8195-smi-larb             [    0                =           0   U           X       X            apb smi         G   (                j      larb@16014000             mediatek,mt8195-smi-larb             [    @                =           0   V           Y       Y            apb smi         G   (   !            O      larb@16015000             mediatek,mt8195-smi-larb             [    P                =           0   U           Z       Z            apb smi         G   (   !            o      clock-controller@1604f000             mediatek,mt8195-camsys_rawa          [                                   W      clock-controller@1606f000             mediatek,mt8195-camsys_yuva          [                                   X      clock-controller@1608f000             mediatek,mt8195-camsys_rawb          [                                   Y      clock-controller@160af000             mediatek,mt8195-camsys_yuvb          [    
                               Z      clock-controller@16140000             mediatek,mt8195-camsys_mraw          [                                    [      larb@16141000             mediatek,mt8195-smi-larb             [                    =           0   U           $       [       $           apb smi gals            G   (   "            n      larb@16142000             mediatek,mt8195-smi-larb             [                     =           0   V           [       [            apb smi         G   (   "            N      clock-controller@17200000             mediatek,mt8195-ccusys           [                                     \      larb@17201000             mediatek,mt8195-smi-larb             [                     =           0   V           \       \            apb smi         G   (               J      larb@1800d000             mediatek,mt8195-smi-larb             [                     =           0   P                              apb smi         G   (               m      larb@1800e000             mediatek,mt8195-smi-larb             [                     =           0   ]                             apb smi         G   (               M      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc          [                                          larb@1802e000             mediatek,mt8195-smi-larb             [                    =           0   P                              apb smi         G   (               l      clock-controller@1802f000             mediatek,mt8195-vdecsys          [                                         larb@1803e000             mediatek,mt8195-smi-larb             [                    =           0   ]                              apb smi         G   (               L      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1            [                                          clock-controller@190f3000             mediatek,mt8195-apusys_pll           [    0                         clock-controller@1a000000             mediatek,mt8195-vencsys          [                                     ^      larb@1a010000             mediatek,mt8195-smi-larb             [                     =           0   P           ^      ^           apb smi         G   (               k      clock-controller@1b000000             mediatek,mt8195-vencsys_core1            [                                     `      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon             [                    `   _                                    larb@1b010000             mediatek,mt8195-smi-larb             [                     =           0   @           `       `                  apb smi gals            G   (               K      ovl@1c000000          2    mediatek,mt8195-disp-ovl mediatek,mt8183-disp-ovl            [                      G      |               G   (                          ]   a           d   _                rdma@1c002000             mediatek,mt8195-disp-rdma            [                      G      ~               G   (                         ]   a            d   _                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color            [     0                G                     G   (                         d   _     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr            [     @                G                     G   (                         d   _     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal            [     P                G                     G   (                         d   _     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma            [     `                G                     G   (                         d   _     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither          [     p                G                     G   (                 	        d   _     p          dsc@1c009000              mediatek,mt8195-disp-dsc             [                     G                     G   (                         d   _               merge@1c014000            mediatek,mt8195-disp-merge           [    @                G                     G   (                         d   _     @          mutex@1c016000            mediatek,mt8195-disp-mutex           [    `                G                     G   (                         |  U      larb@1c018000             mediatek,mt8195-smi-larb             [                    =            0   P              (      (              apb smi gals            G   (               b      larb@1c019000             mediatek,mt8195-smi-larb             [                    =           0   @              (                     apb smi gals            G   (               B      syscon@1c100000           mediatek,mt8195-vdosys1 syscon           [                                    !      smi@1c01b000              mediatek,mt8195-smi-common-vdo           [                           %      &      )      $        apb smi gals0 gals1         G   (               P      iommu@1c01f000            mediatek,mt8195-iommu-vdo            [                  8  N   b   c   d   e   f   g   h   i   j   k   l   m   n   o        G                     .                 '        bclk            G   (               a      larb@1c102000             mediatek,mt8195-smi-larb             [                     =           0   P           !       !       !           apb smi gals            G   (               c      larb@1c103000             mediatek,mt8195-smi-larb             [    0                =           0   @           !      !                  apb smi gals            G   (               C         chosen          serial0:921600n8          memory@40000000          Omemory           [    @                   	compatible interrupt-parent #address-cells #size-cells model gce0 gce1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts cpus num-channels wakeup-delay-ms mediatek,platform status #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up mediatek,drive-strength-adv drive-strength bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 #io-channel-cells phys mediatek,syscon-wakeup wakeup-source usb2-lpm-disable spi-max-frequency bits #phy-cells nvmem-cells nvmem-cell-names mediatek,smi mediatek,larb-id mediatek,larbs iommus mediatek,gce-client-reg mediatek,gce-events stdout-path 