     8     (                                           t    google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192                                  +            7Google Spherion (rev0 - 3)     aliases          =/soc/ovl@14005000            B/soc/ovl@14006000            J/soc/ovl@14014000            R/soc/rdma@14007000           X/soc/rdma@14015000           ^/soc/serial@11002000          fixed-factor-clock-13m            fixed-factor-clock           f             s            z                        clk13m              $      oscillator0           fixed-clock          f                      clk26m                    oscillator1           fixed-clock          f                         clk32k        cpus                         +       cpu@0            cpu           arm,cortex-a55                        psci             ec3@                                                                 
      cpu@100          cpu           arm,cortex-a55                       psci             ec3@                                                                       cpu@200          cpu           arm,cortex-a55                       psci             ec3@                                                                       cpu@300          cpu           arm,cortex-a55                       psci             ec3@                                                                       cpu@400          cpu           arm,cortex-a76                       psci             f                           	                                            cpu@500          cpu           arm,cortex-a76                       psci             f                           	                                            cpu@600          cpu           arm,cortex-a76                       psci             f                           	                                            cpu@700          cpu           arm,cortex-a76                       psci             f                           	                                            cpu-map    cluster0       core0               
      core1                     core2                     core3                     core4                     core5                     core6                     core7                           l2-cache0             cache                                 l2-cache1             cache                           	      l3-cache              cache                     idle-states         $psci       cpu-sleep-l           arm,idle-state          1           H        Y   7        j           z                    cpu-sleep-b           arm,idle-state          1           H        Y   #        j           z                    cluster-sleep-l           arm,idle-state          1          H        Y   <        j           z  \                  cluster-sleep-b           arm,idle-state          1          H        Y   (        j           z                          pmu-a55           arm,cortex-a55-pmu                                        pmu-a76           arm,cortex-a76-pmu                                        psci              arm,psci-1.0             smc       timer             arm,armv8-timer                   @                                               
                 ]@      soc                      +             simple-bus              performance-controller@11bc10             mediatek,cpufreq-hw                            0                                    interrupt-controller@c000000              arm,gic-v3                                                                                                 	                      ppi-partitions     interrupt-partition-0              
                           interrupt-partition-1                                               syscon@10000000            mediatek,mt8192-topckgen syscon                                 f                     syscon@10001000            mediatek,mt8192-infracfg syscon                                f                                syscon@10003000           mediatek,mt8192-pericfg syscon                0                 f               .      pinctrl@10005000              mediatek,mt8192-pinctrl               P                                                                                                                                                ]  
iocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint                     $           0                                                             	  <I2S_DP_LRCK IS_DP_BCLK I2S_DP_MCLK I2S_DP_DATAOUT SAR0_INT_ODL EC_AP_INT_ODL EDPBRDG_INT_ODL DPBRDG_INT_ODL DPBRDG_PWREN DPBRDG_RST_ODL I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAIN AP_FLASH_WP_L TRACKPAD_INT_ODL EC_AP_HPD_OD SD_CD_ODL HP_INT_ODL_ALC EN_PP1000_DPBRDG AP_GPIO20 TOUCH_INT_L_1V8 UART_BT_WAKE_ODL AP_GPIO23 AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK EN_PP3300_DPBRDG_DX AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO I2S_HP_DATAOUT AP_GPIO30 I2S_SPKR_MCLK I2S_SPKR_BCLK I2S_SPKR_LRCK I2S_SPKR_DATAIN I2S_SPKR_DATAOUT AP_SPI_H1_TPM_CLK AP_SPI_H1_TPM_CS_L AP_SPI_H1_TPM_MISO AP_SPI_H1_TPM_MOSI BL_PWM EDPBRDG_PWREN EDPBRDG_RST_ODL EN_PP3300_HUB HUB_RST_L       SD_CLK SD_CMD SD_DATA3 SD_DATA0 SD_DATA2 SD_DATA1       PCIE_WAKE_ODL PCIE_RST_L PCIE_CLKREQ_ODL                        SPMI_SCL SPMI_SDA AP_GOOD UART_DBG_TX_AP_RX UART_AP_TX_DBG_RX UART_AP_TX_BT_RX UART_BT_TX_AP_RX MIPI_DPI_D0_R MIPI_DPI_D1_R MIPI_DPI_D2_R MIPI_DPI_D3_R MIPI_DPI_D4_R MIPI_DPI_D5_R MIPI_DPI_D6_R MIPI_DPI_D7_R MIPI_DPI_D8_R MIPI_DPI_D9_R MIPI_DPI_D10_R   MIPI_DPI_DE_R MIPI_DPI_D11_R MIPI_DPI_VSYNC_R MIPI_DPI_CLK_R MIPI_DPI_HSYNC_R PCM_BT_DATAIN PCM_BT_SYNC PCM_BT_DATAOUT PCM_BT_CLK AP_I2C_AUDIO_SCL AP_I2C_AUDIO_SDA SCP_I2C_SCL SCP_I2C_SDA AP_I2C_WLAN_SCL AP_I2C_WLAN_SDA AP_I2C_DPBRDG_SCL AP_I2C_DPBRDG_SDA EN_PP1800_DPBRDG_DX EN_PP3300_EDP_DX EN_PP1800_EDPBRDG_DX EN_PP1000_EDPBRDG SCP_JTAG0_TDO SCP_JTAG0_TDI SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TRSTN EN_PP3000_VMC_PMU EN_PP3300_DISPLAY_DX TOUCH_RST_L_1V8 TOUCH_REPORT_DISABLE   AP_I2C_TRACKPAD_SCL_1V8 AP_I2C_TRACKPAD_SDA_1V8 EN_PP3300_WLAN BT_KILL_L WIFI_KILL_L SET_VMC_VOLT_AT_1V8 EN_SPK AP_WARM_RST_REQ   EN_PP3000_SD_S3 AP_EDP_BKLTEN    AP_SPI_EC_CLK AP_SPI_EC_CS_L AP_SPI_EC_MISO AP_SPI_EC_MOSI AP_I2C_EDPBRDG_SCL AP_I2C_EDPBRDG_SDA MT6315_PROC_INT MT6315_GPU_INT UART_SERVO_TX_SCP_RX UART_SCP_TX_SERVO_RX BT_RTS_AP_CTS AP_RTS_BT_CTS UART_AP_WAKE_BT_ODL WLAN_ALERT_ODL EC_IN_RW_ODL H1_AP_INT_ODL            MSDC0_CMD MSDC0_DAT0 MSDC0_DAT2 MSDC0_DAT4 MSDC0_DAT6 MSDC0_DAT1 MSDC0_DAT5 MSDC0_DAT7 MSDC0_DSL MSDC0_CLK MSDC0_DAT3 MSDC0_RST_L SCP_VREQ_VAO AUD_DAT_MOSI2 AUD_NLE_MOSI1 AUD_NLE_MOSI0 AUD_DAT_MISO2 AP_I2C_SAR_SDA AP_I2C_SAR_SCL AP_I2C_PWR_SCL AP_I2C_PWR_SDA AP_I2C_TS_SCL_1V8 AP_I2C_TS_SDA_1V8 SRCLKENA0 SRCLKENA1 AP_EC_WATCHDOG_L PWRAP_SPI0_MI PWRAP_SPI0_CSN PWRAP_SPI0_MO PWRAP_SPI0_CK AP_RTC_CLK32K AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1                cr50-irq-default-pins               (   pins-gsc-ap-int-odl         L            S         cros-ec-irq-default-pins                &   pins-ec-ap-int-odl          L            S         `         i2c0-default-pins               C   pins-bus            L            `           m           i2c1-default-pins               =   pins-bus            L  v  w        `           m           i2c2-default-pins               >   pins-bus            L            `            i2c3-default-pins               9   pins-bus            L                     m           i2c7-default-pins               ;   pins-bus            L  |  }                 m           mmc0-default-pins               F   pins-cmd-dat          $  L                           S                   `   e      pins-clk            L                        f      pins-rst            L                        e         mmc0-uhs-pins               G   pins-cmd-dat          $  L                           S           
        `   e      pins-clk            L             
           f      pins-rst            L                        e      pins-ds         L             
           f         mmc1-default-pins               J   pins-cmd-dat            L  6  8  7  5  4         S                   `   e      pins-clk            L  3                      f      pins-insert         L            S         `         mmc1-uhs-pins               K   pins-cmd-dat            L  6  8  7  5  4         S                   `   e      pins-clk            L  3         S                      f         nor-flash-default-pins              7   pins-cs-io1         L             S         `           
      pins-io0            L           `           
      pins-clk            L           S         `           
         pcie-default-pins               5   pins-pcie-wake          L  ?         `      pins-pcie-pereset           L  @      pins-pcie-clkreq            L  A         `      pins-wifi-kill          L                     pp3300-wlan-pins                c   pins-pcie-en-pp3300-wlan            L                     scp-pins                *   pins-vreq-vao           L           spi1-default-pins               %   pins-cs-mosi-clk            L                     pins-miso           L                    spi5-default-pins               '   pins-bus            L  &  %   '  $                  trackpad-default-pins               ?   pins-int-n          L            S        `   g         touchscreen-default-pins                D   pins-irq            L            S         `      pins-reset          L                  pins-report-sw          L                        syscon@10006000       )    mediatek,mt8192-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8192-power-controller                         +                           2   power-domain@0                        s            :      /        audio audio1 audio2                              power-domain@1                       s              conn                                 power-domain@2                       s              mfg                      +                  power-domain@3                                              +                  power-domain@4                                power-domain@5                                power-domain@6                                power-domain@7                                power-domain@8                                      power-domain@9              	      (   s                                    !  disp disp-0 disp-1 disp-2 disp-3                                    +                  power-domain@10             
      (   s                                       ipe ipe-0 ipe-1 ipe-2 ipe-3                              power-domain@11                      s                           isp isp-0 isp-1                              power-domain@12                      s                           isp2 isp2-0 isp2-1                               power-domain@13                      s                  
  mdp mdp-0                                power-domain@14                      s      3              venc venc-0                              power-domain@15                       s      4                           vdec vdec-0 vdec-1 vdec-2                                   +                  power-domain@16                      s                           vdec2-0 vdec2-1 vdec2-2                      power-domain@17                   (   s      
                                     cam cam-0 cam-1 cam-2 cam-3                                 +                  power-domain@18                      s   !            cam_rawa-0                    power-domain@19                      s   "            cam_rawb-0                    power-domain@20                      s   #            cam_rawc-0                                watchdog@10007000             mediatek,mt8192-wdt               p                               1      syscon@1000c000       "    mediatek,mt8192-apmixedsys syscon                                  f               -      timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer              p                                       s   $      pwrap@10026000            mediatek,mt6873-pwrap                `                
pwrap                                  s                   	  spi wrap                          	         pmic              mediatek,mt6359                                          mt6359codec         4           G           [         regulators     buck_vs1            ovs1         ~ 5          !                           buck_vgpu11         ovgpu11          ~          7                                                      buck_vmodem         ovmodem          ~                    *                 buck_vpu            ovpu         ~          7                                             buck_vcore          ovcore           ~                                                        buck_vs2            ovs2         ~ 5          j                            buck_vpa            ovpa         ~           7          ,      buck_vproc2         ovproc2          ~          7          L                                   buck_vproc1         ovproc1          ~          7          L                                   buck_vcore_sshub            ovcore_sshub         ~          7      buck_vgpu11_sshub           ovgpu11_sshub            ~                         ldo_vaud18          ovaud18          ~ w@         w@                 ldo_vsim1           ovsim1           ~          /M`      ldo_vibr            ovibr            ~ O         2Z      ldo_vrf12           ovrf12           ~                          ldo_vusb            ovusb            ~ -         -                         ldo_vsram_proc2         ovsram_proc2         ~                     L                          ldo_vio18           ovio18           ~                                   ldo_vcamio          ovcamio          ~                ldo_vcn18           ovcn18           ~ w@         w@                 ldo_vfe28           ovfe28           ~ *         *           x      ldo_vcn13           ovcn13           ~                 ldo_vcn33_1_bt          ovcn33_1_bt          ~ *         5g      ldo_vcn33_1_wifi            ovcn33_1_wifi            ~ *         5g      ldo_vaux18          ovaux18          ~ w@         w@                          ldo_vsram_others            ovsram_others            ~                                      ldo_vefuse          ovefuse          ~                ldo_vxo22           ovxo22           ~ w@         !               ldo_vrfck           ovrfck           ~ `               ldo_vrfck_1         ovrfck           ~          j       ldo_vbif28          ovbif28          ~ *         *                 ldo_vio28           ovio28           ~ *         2Z               ldo_vemc            ovemc            ~ ,@          2Z      ldo_vemc_1          ovemc            ~ &%         2Z            H      ldo_vcn33_2_bt          ovcn33_2_bt          ~ *         5g      ldo_vcn33_2_wifi            ovcn33_2_wifi            ~ *         5g      ldo_va12            ova12            ~ O                         ldo_va09            ova09            ~ 5          O      ldo_vrf18           ovrf18           ~          P      ldo_vsram_md          	  ovsram_md            ~                     *                 ldo_vufs            ovufs            ~                               I      ldo_vm18            ovm18            ~                         ldo_vbbck           ovbbck           ~          O      ldo_vsram_proc1         ovsram_proc1         ~                     L                          ldo_vsim2           ovsim2           ~          /M`      ldo_vsram_others_sshub          ovsram_others_sshub          ~                    mt6359rtc             mediatek,mt6358-rtc             spmi@10027000             mediatek,mt6873-spmi                  p                            
pmif spmimst             s                   8      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux                       	                           +       pmic@6            mediatek,mt6315-regulator                      regulators     vbuck1          vbuck1          oVbcpu           ~          7                                            vbuck3          vbuck3          oVlcpu           ~          7                                                  pmic@7            mediatek,mt6315-regulator                      regulators     vbuck1          vbuck1          oVgpu            ~ 	@*         5                                             mailbox@10228000              mediatek,mt8192-gce              "       @                                            s              gce             N      clock-controller@10720000             mediatek,mt8192-scp_adsp                 r                  f           ,fail          serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart                                         m                s               	  baud bus            ,okay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart                 0                       n                s               	  baud bus          	  ,disabled          clock-controller@11007000             mediatek,mt8192-imp_iic_wrap_c                p                 f         spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M                    parent-clk sel-clk spi-clk        	  ,disabled          pwm@1100e000              mediatek,mt8183-disp-pwm                                                        3            s      !      8        main mm       	  ,disabled          spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M            <        parent-clk sel-clk spi-clk          ,okay            >            Rdefault         `   %   ec@0              google,cros-ec-spi                                         j -        Rdefault         `   &                     +       cbas              google,cros-cbas          pwm           google,cros-ec-pwm          3           ,okay                d      i2c-tunnel            google,cros-ec-i2c-tunnel           |                         +       sbs-battery@b             sbs,sbs-battery                                            regulator@0           google,cros-ec-regulator                         ~ w@         2Z            M      regulator@1           google,cros-ec-regulator                        ~ 2Z         2Z            L      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector                      left            dual            host            source        connector@1           usb-c-connector                     right           dual            host            source           keyboard-controller           google,cros-ec-keyb                                     D     t x c  	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (  +               	  	                 spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                         s      M            >        parent-clk sel-clk spi-clk        	  ,disabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                 0                                       s      M            ?        parent-clk sel-clk spi-clk        	  ,disabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            L        parent-clk sel-clk spi-clk        	  ,disabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            M        parent-clk sel-clk spi-clk          ,okay            @      %           >            Rdefault         `   '   cr50@0            google,cr50                                        j B@        Rdefault         `   (         spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            m        parent-clk sel-clk spi-clk        	  ,disabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                                        s      M            n        parent-clk sel-clk spi-clk        	  ,disabled          scp@10500000              mediatek,mt8192-scp       0       P             r             p                 
sram cfg l1tcm                                s              main            ,okay            Imediatek/mt8192/scp.img         W   )        Rdefault         `   *            a   cros-ec           google,cros-ec-rpmsg            ecros-ec-rpmsg            usb@11200000          '    mediatek,mt8192-xhci mediatek,mtk-xhci                               >              	  
mac ippc                       a               yhost               +      ,                 "      #        	      ]      ]          s      7   -               R      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck                     .      f        ,okay               /           0      syscon@11210000           mediatek,mt8192-audsys syscon                !                   f               3   mt8192-afe-pcm            mediatek,mt8192-audio                                    1         	  audiosys               -                                 2            s   3       3      3      3      3      3      3      3      3      3      3   	   3   
   3      3      3      3      3      3      3      3         /      :                  H      /      e      0      i      +      g      ,      k      ;      <      =      >      ?      @      A      B      C      D                                                                        7        u  aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adda6_adc_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_tdm_clk aud_tml_clk aud_nle aud_dac_hires_clk aud_adc_hires_clk aud_adc_hires_tml aud_adda6_adc_hires_clk aud_3rd_dac_clk aud_3rd_dac_predis_clk aud_3rd_dac_tml aud_3rd_dac_hires_clk aud_infra_clk aud_infra_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d4_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d4 top_mux_aud_eng2 top_apll2_d4 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_i2s6_m_sel top_i2s7_m_sel top_i2s8_m_sel top_i2s9_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_apll12_div5 top_apll12_div6 top_apll12_div7 top_apll12_div8 top_apll12_div9 top_mux_audio_h top_clk26m_clk             pcie@11230000             mediatek,mt8192-pcie             pci              #                	  
pcie-mac                         +         0   s      +      '      *      j      ^      \      /  pl_250m tl_26m tl_96m tl_32k peri_26m top_133m                )        	      Q                                           8                                                                                        `  1                  4                      4                     4                     4           Rdefault         `   5   interrupt-controller                                                 4      pcie@0,0             pci                                      ?                                      +               wifi@0,0          (                                              W   6            spi@11234000              mediatek,mt8192-nor              #@                                      s      :      w      ]        spi sf axi                :        	      b                     +            ,okay            Rdefault         `   7   flash@0            winbond,w25q64jwm jedec,spi-nor                      ju         I           Z            efuse@11c10000        %    mediatek,mt8192-efuse mediatek,efuse                                               +      data1@1c0                 X      calib@580                 h         i2c@11cb0000              mediatek,mt8192-i2c                            !s                       s                s   8          x      	  main dma             z                        +            ,okay                      Rdefault         `   9      clock-controller@11cb1000             mediatek,mt8192-imp_iic_wrap_e                                f               8      i2c@11d00000              mediatek,mt8192-i2c                            !v                      w                s   :          x      	  main dma             z                        +            ,okay                      Rdefault         `   ;      i2c@11d01000              mediatek,mt8192-i2c                           !w                     x                s   :         x      	  main dma             z                        +          	  ,disabled          i2c@11d02000              mediatek,mt8192-i2c                            !y                      y                s   :         x      	  main dma             z                        +          	  ,disabled          clock-controller@11d03000             mediatek,mt8192-imp_iic_wrap_s               0                 f               :      i2c@11d20000              mediatek,mt8192-i2c                            !q                       q                s   <          x      	  main dma             z                        +            ,okay                      Rdefault         `   =      i2c@11d21000              mediatek,mt8192-i2c                           !q                     r                s   <         x      	  main dma             z                        +            ,okay                      k  18        Rdefault         `   >   trackpad@15           elan,ekth3000                                         Rdefault         `   ?        |   @                  i2c@11d22000              mediatek,mt8192-i2c                            !s                     t                s   <         x      	  main dma             z                        +          	  ,disabled          clock-controller@11d23000              mediatek,mt8192-imp_iic_wrap_ws              0                 f               <      i2c@11e00000              mediatek,mt8192-i2c                            !u                       u                s   A          x      	  main dma             z                        +          	  ,disabled          clock-controller@11e01000             mediatek,mt8192-imp_iic_wrap_w                                f               A      t-phy@11e40000        .    mediatek,mt8192-tphy mediatek,generic-tphy-v2                        +                           usb-phy@0                            s           ref                        +      usb-phy@700               	          s           ref                        ,         dsi-phy@11e50000              mediatek,mt8183-mipi-tx                                s   -   
         f                         mipi_tx0_pll          	  ,disabled                Q      i2c@11f00000              mediatek,mt8192-i2c                            !p                      p                s   B          x      	  main dma             z                        +            ,okay                      Rdefault         `   C   touchscreen@10                                        Rdefault         `   D          elan,ekth3500            i2c@11f01000              mediatek,mt8192-i2c                           !u                      v                s   B         x      	  main dma             z                        +          	  ,disabled          clock-controller@11f02000             mediatek,mt8192-imp_iic_wrap_n                                 f               B      clock-controller@11f10000             mediatek,mt8192-msdc_top                                   f               E      mmc@11f60000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                                    c             8   s         E   	   E      E      E      E      E         3  source hclk source_cg sys_cg pclk_cg axi_cg ahb_cg          ,okay            Rdefault state_uhs           `   F           G        P           n            H           I                                                               (         ,         4         :      mmc@11f70000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                                    g             8   s         E   
   E      E      E      E      E         3  source hclk source_cg sys_cg pclk_cg axi_cg ahb_cg          ,okay            Rdefault state_uhs           `   J           K        P           n         H                    L           M         Q         b         o         ,         }      clock-controller@13fbf000             mediatek,mt8192-mfgcfg                                f         syscon@14000000           mediatek,mt8192-mmsys syscon                                    f                         N          N                 N                            mutex@14001000            mediatek,mt8192-disp-mutex                                                       s                              2   	      smi@14002000              mediatek,mt8192-smi-common                                   s                                apb smi gals0 gals1            2   	            O      larb@14003000             mediatek,mt8192-smi-larb                  0                               O         s              apb smi            2   	            R      larb@14004000             mediatek,mt8192-smi-larb                  @                              O         s              apb smi            2   	            S      ovl@14005000              mediatek,mt8192-disp-ovl                  P                                       s                 P      P              2   	           N     P          ovl@14006000              mediatek,mt8192-disp-ovl-2l               `                                         2   	         s                 P   "   P               N     `          rdma@14007000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma               p                                       s                 P                         2   	           N     p          color@14009000        6    mediatek,mt8192-disp-color mediatek,mt8173-disp-color                                                         2   	         s                 N               ccorr@1400a000            mediatek,mt8192-disp-ccorr                                                        2   	         s      	           N               aal@1400b000          2    mediatek,mt8192-disp-aal mediatek,mt8183-disp-aal                                                         2   	         s                 N               gamma@1400c000        6    mediatek,mt8192-disp-gamma mediatek,mt8183-disp-gamma                                                         2   	         s                 N               postmask@1400d000             mediatek,mt8192-disp-postmask                                                         2   	         s                 N               dither@1400e000       8    mediatek,mt8192-disp-dither mediatek,mt8183-disp-dither                                                       2   	         s      
           N               dsi@14010000              mediatek,mt8183-dsi                                     	                s                Q        engine digital hs              Q        dphy               2   	                    	  ,disabled       port       endpoint                ovl@14014000              mediatek,mt8192-disp-ovl-2l              @                                        2   	         s                 P   #   P   !           N     @          rdma@14015000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma              P                                        2   	         s                 P   %                      N     P          dpi@14016000              mediatek,mt8192-dpi              `                                      s      !         -           pixel engine pll          	  ,disabled          m4u@1401d000              mediatek,mt8192-m4u                            <     R   S   T   U   V   W   X   Y   Z   [   \   ]   ^   _   `                              s              bclk               2   	                       P      clock-controller@15020000             mediatek,mt8192-imgsys                                 f                     larb@1502e000             mediatek,mt8192-smi-larb                                    	           O         s                      apb smi            2               X      clock-controller@15820000             mediatek,mt8192-imgsys2                                f                     larb@1582e000             mediatek,mt8192-smi-larb                                               O         s                      apb smi            2               Y      larb@1600d000             mediatek,mt8192-smi-larb                                                O         s                      apb smi            2               V      clock-controller@1600f000             mediatek,mt8192-vdecsys_soc                                f                     larb@1602e000             mediatek,mt8192-smi-larb                                               O         s                      apb smi            2               U      clock-controller@1602f000             mediatek,mt8192-vdecsys                               f                     clock-controller@17000000             mediatek,mt8192-vencsys                                 f                     larb@17010000             mediatek,mt8192-smi-larb                                                O         s                     apb smi            2               W      vcodec@17020000           mediatek,mt8192-vcodec-enc                               X     P      P      P      P      P      P      P      P      P      P      P                 5                  a           2            s            
  venc-set1                 3        	      W      clock-controller@1a000000             mediatek,mt8192-camsys                                  f                      larb@1a001000             mediatek,mt8192-smi-larb                                                O         s                       apb smi            2               Z      larb@1a002000             mediatek,mt8192-smi-larb                                                 O         s                      apb smi            2               [      larb@1a00f000             mediatek,mt8192-smi-larb                                                O         s   !      !            apb smi            2               \      larb@1a010000             mediatek,mt8192-smi-larb                                                O         s   "      "            apb smi            2               ]      larb@1a011000             mediatek,mt8192-smi-larb                                               O         s   #       #           apb smi            2               ^      clock-controller@1a04f000             mediatek,mt8192-camsys_rawa                               f               !      clock-controller@1a06f000             mediatek,mt8192-camsys_rawb                               f               "      clock-controller@1a08f000             mediatek,mt8192-camsys_rawc                               f               #      clock-controller@1b000000             mediatek,mt8192-ipesys                                  f                     larb@1b00f000             mediatek,mt8192-smi-larb                                                O         s                    apb smi            2   
            `      larb@1b10f000             mediatek,mt8192-smi-larb                                               O         s                     apb smi            2   
            _      clock-controller@1f000000             mediatek,mt8192-mdpsys                                  f                     larb@1f002000             mediatek,mt8192-smi-larb                                                 O         s                    apb smi            2               T         chosen          'serial0:115200n8          memory@40000000          memory               @                regulator-1v8-g           regulator-fixed         opp1800_ldo_g                      3        ~ w@         w@        E   /      regulator-3v3-g           regulator-fixed       	  opp3300_g                      3        ~ 2Z         2Z        E   b            /      regulator-3v3-z           regulator-fixed         opp3300_ldo_z                      3        ~ 2Z         2Z        E   b      regulator-3v3-u           regulator-fixed       	  opp3300_u                      3        ~ 2Z         2Z        E   /            @      regulator-3v3-wlan            regulator-fixed         opp3300_wlan                   3        ~ 2Z         2Z        Rdefault         `   c         P        c                regulator-5v0-a           regulator-fixed       	  opp5000_a                      3        ~ LK@         LK@        E   b            0      regulator-var-sys             regulator-fixed       
  oppvar_sys                     3            b      reserved-memory                      +               scp@50000000              shared-dma-pool              P                  h            )      wifi@c0000000             restricted-dma-pool                                    6         pwmleds       	    pwm-leds       led         okbd_backlight           x            ~   d                          	compatible interrupt-parent #address-cells #size-cells model ovl0 ovl-2l0 ovl-2l2 rdma0 rdma4 serial0 #clock-cells clocks clock-div clock-mult clock-output-names phandle clock-frequency device_type reg enable-method cpu-idle-states next-level-cache performance-domains capacity-dmips-mhz cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux input-enable bias-pull-up drive-strength-microamp bias-disable drive-strength bias-pull-down output-high output-low #power-domain-cells clock-names mediatek,infracfg assigned-clocks assigned-clock-parents interrupts-extended mediatek,dmic-mode mediatek,mic-type-0 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-compatible #mbox-cells status #pwm-cells mediatek,pad-select pinctrl-names pinctrl-0 spi-max-frequency google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count label power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap cs-gpios firmware-name memory-region mediatek,rpmsg-name interrupt-names phys wakeup-source mediatek,syscon-wakeup vusb33-supply vbus-supply resets reset-names mediatek,apmixedsys mediatek,topckgen power-domains bus-range interrupt-map-mask interrupt-map num-lanes spi-rx-bus-width spi-tx-bus-width clock-stretch-ns vcc-supply #phy-cells pinctrl-1 vmmc-supply vqmmc-supply cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset mmc-hs400-enhanced-strobe hs400-ds-delay no-sdio no-sd non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc mboxes mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus mediatek,rdma-fifo-size phy-names mediatek,larbs #iommu-cells mediatek,scp stdout-path regulator-boot-on vin-supply enable-active-high gpio no-map function color pwms max-brightness 