  B2   8  ?(   (            
  >                             $    mediatek,mt8186-evb mediatek,mt8186                                  +         !   7MediaTek MT8186 evaluation board       cpus                         +       cpu-map    cluster0       core0            =         core1            =         core2            =         core3            =         core4            =         core5            =         core6            =         core7            =   	            cpu@0            Acpu           arm,cortex-a55           M             Qpsci             _w5          o  ~            
                                             cpu@100          Acpu           arm,cortex-a55           M            Qpsci             _w5          o  ~            
                                             cpu@200          Acpu           arm,cortex-a55           M            Qpsci             _w5          o  ~            
                                             cpu@300          Acpu           arm,cortex-a55           M            Qpsci             _w5          o  ~            
                                             cpu@400          Acpu           arm,cortex-a55           M            Qpsci             _w5          o  ~            
                                             cpu@500          Acpu           arm,cortex-a55           M            Qpsci             _w5          o  ~            
                                             cpu@600          Acpu           arm,cortex-a76           M            Qpsci             _z0         o                                                            cpu@700          Acpu           arm,cortex-a76           M            Qpsci             _z0         o                                                      	      idle-states          psci       cpu-off-l             arm,idle-state                                   2            d          @            
      cpu-off-b             arm,idle-state                                   2            d          x                  cluster-off-l             arm,idle-state                                  d                      4                  cluster-off-b             arm,idle-state                                  d                      l                     l2-cache0             cache                                 l2-cache1             cache                                 l3-cache              cache                        fixed-factor-clock-13m            fixed-factor-clock          !            .           5           ?           Jclk13m                    oscillator-26m            fixed-clock         !             _        Jclk26m                    oscillator-32k            fixed-clock         !             _           Jclk32k        pmu-a55           arm,cortex-a55-pmu                      ]                  pmu-a76           arm,cortex-a76-pmu                      ]                  psci              arm,psci-1.0             Xsmc       timer             arm,armv8-timer                   @  ]                                             
             soc                      +             simple-bus           h   interrupt-controller@c000000              arm,gic-v3          o                                             M                                    ]      	                      ppi-partitions     interrupt-partition-0                                               interrupt-partition-1                 	                        syscon@c53a000            mediatek,mt8186-mcusys syscon            M    S                !         syscon@10000000            mediatek,mt8186-topckgen syscon          M                      !                     syscon@10001000       #    mediatek,mt8186-infracfg_ao syscon           M                     !                                syscon@10003000           mediatek,mt8186-pericfg syscon           M     0              pinctrl@10005000              mediatek,mt8186-pinctrl          M     P                           "             $             &             *             ,                           B  iocfg0 iocfg_lt iocfg_lm iocfg_lb iocfg_bl iocfg_rb iocfg_rt eint                                                              ]                      o                  i2c0-default-pins                  pins-bus                                                      i2c1-default-pins                  pins-bus                                                      i2c2-default-pins                  pins-bus                                                      i2c3-default-pins                  pins-bus                                                      i2c4-default-pins                  pins-bus                                                      i2c5-default-pins                  pins-bus                                                      i2c6-default-pins                  pins-bus                        -                                i2c7-default-pins                   pins-bus                                                      i2c8-default-pins               !   pins-bus                                                      i2c9-default-pins               "   pins-bus                        -                                   watchdog@10007000             mediatek,mt8186-wdt          :         M     p                         syscon@1000c000       "    mediatek,mt8186-apmixedsys syscon            M                     !               #      pwrap@1000d000            mediatek,mt8186-pwrap syscon             M                     pwrap           ]                      .                   	  Rspi wrap          timer@10017000        ,    mediatek,mt8186-timer mediatek,mt6765-timer          M    p                ]                      .         scp@10500000              mediatek,mt8186-scp           M    P             \             	  sram cfg            ]                    spi@11000000              mediatek,mt8186-nor          M                       .      3      O      c      d        Rspi sf axi axi_s            ^      3        n      X        ]      %             	  disabled          adc@11001000          .    mediatek,mt8186-auxadc mediatek,mt8173-auxadc            M                                .      "        Rmain          serial@11002000       *    mediatek,mt8186-uart mediatek,mt6577-uart            M                      ]       p               .               	  Rbaud bus            okay          serial@11003000       *    mediatek,mt8186-uart mediatek,mt6577-uart            M     0                ]       q               .               	  Rbaud bus          	  disabled          i2c@11007000              mediatek,mt8186-i2c           M     p                             ]       i               .             '      	  Rmain dma            5                        +            okay             _         default                  i2c@11008000              mediatek,mt8186-i2c           M                                  ]       j               .            '      	  Rmain dma            5                        +            okay             _           @        default                  i2c@11009000              mediatek,mt8186-i2c           M                                 ]       k               .            '      	  Rmain dma            5                        +            okay             _           '        default                  i2c@1100f000              mediatek,mt8186-i2c           M                                 ]       l               .            '      	  Rmain dma            5                        +            okay             _         default                  i2c@11011000              mediatek,mt8186-i2c           M                               ]       m               .            '      	  Rmain dma            5                        +            okay             _         default                  i2c@11016000              mediatek,mt8186-i2c           M    `                             ]      b               .            '      	  Rmain dma            5                        +            okay             _         default                  i2c@1100d000              mediatek,mt8186-i2c           M                                  ]      c               .            '      	  Rmain dma            5                        +            okay             _         default                  i2c@11004000              mediatek,mt8186-i2c           M     @             	               ]       n               .            '      	  Rmain dma            5                        +            okay             _         default                   i2c@11005000              mediatek,mt8186-i2c           M     P             
              ]       o               .            '      	  Rmain dma            5                        +            okay             _         default            !      spi@1100a000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             M                     ]                      .      K                    Rparent-clk sel-clk spi-clk        	  disabled          pwm@1100e000          2    mediatek,mt8186-disp-pwm mediatek,mt8183-disp-pwm            M                     ]                                 .            4        Rmain mm       	  disabled          spi@11010000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             M                     ]                      .      K            8        Rparent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             M                     ]                      .      K            ;        Rparent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             M    0                ]                      .      K            <        Rparent-clk sel-clk spi-clk        	  disabled          spi@11014000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             M    @                ]       t               .      K            J        Rparent-clk sel-clk spi-clk        	  disabled          spi@11015000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +             M    P                ]       u               .      K            K        Rparent-clk sel-clk spi-clk        	  disabled          clock-controller@11017000             mediatek,mt8186-imp_iic_wrap             M    p                !                     serial@11018000       *    mediatek,mt8186-uart mediatek,mt6577-uart            M                    ]                      .               	  Rbaud bus          	  disabled          i2c@11019000              mediatek,mt8186-i2c           M                                ]      d               .      	      '      	  Rmain dma            5                        +            okay             _         default            "      mmc@11230000          (    mediatek,mt8186-mmc mediatek,mt8183-mmc           M    #                              .                  U        Rsource hclk source_cg           ]       d               ^              n   #         	  disabled          mmc@11240000          (    mediatek,mt8186-mmc mediatek,mt8183-mmc           M    $                              .                  V        Rsource hclk source_cg           ]       e               ^              n      o      	  disabled          t-phy@11c80000        .    mediatek,mt8186-tphy mediatek,generic-tphy-v2                        +           h                     okay       usb-phy@0            M               .           Rref                  usb-phy@700          M     	         .           Rref                     t-phy@11ca0000        .    mediatek,mt8186-tphy mediatek,generic-tphy-v2                        +           h                     okay       usb-phy@0            M               .           Rref                                efuse@11cb0000        %    mediatek,mt8186-efuse mediatek,efuse             M                                  +         dsi-phy@11cc0000              mediatek,mt8183-mipi-tx          M                     .           !                        Jmipi_tx0_pll          	  disabled          clock-controller@13000000             mediatek,mt8186-mfgsys           M                      !         syscon@14000000           mediatek,mt8186-mmsys syscon             M                      !                    clock-controller@14020000             mediatek,mt8186-wpesys           M                     !         clock-controller@15020000             mediatek,mt8186-imgsys1          M                     !         clock-controller@15820000             mediatek,mt8186-imgsys2          M                     !         clock-controller@1602f000             mediatek,mt8186-vdecsys          M                    !         clock-controller@17000000             mediatek,mt8186-vencsys          M                      !         clock-controller@1a000000             mediatek,mt8186-camsys           M                      !         clock-controller@1a04f000             mediatek,mt8186-camsys_rawa          M                    !         clock-controller@1a06f000             mediatek,mt8186-camsys_rawb          M                    !         clock-controller@1b000000             mediatek,mt8186-mdpsys           M                      !         clock-controller@1c000000             mediatek,mt8186-ipesys           M                      !            aliases         /soc/serial@11002000          chosen          serial0:921600n8          memory@40000000          Amemory           M    @                   	compatible interrupt-parent #address-cells #size-cells model cpu device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states next-level-cache #cooling-cells phandle entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us #clock-cells clocks clock-div clock-mult clock-output-names interrupts ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-disable drive-strength-microamp input-enable bias-pull-up mediatek,disable-extrst clock-names assigned-clocks assigned-clock-parents status #io-channel-cells pinctrl-names pinctrl-0 i2c-scl-internal-delay-ns #pwm-cells #phy-cells mediatek,discth serial0 stdout-path 