     8  \   (              $                             `    google,hana-rev6 google,hana-rev5 google,hana-rev4 google,hana-rev3 google,hana mediatek,mt8173                                  +            7Google Hana    aliases          =/soc/ovl@1400c000            B/soc/ovl@1400d000            G/soc/rdma@1400e000           M/soc/rdma@1400f000           S/soc/rdma@14010000           Y/soc/wdma@14011000           _/soc/wdma@14012000           e/soc/color@14013000          l/soc/color@14014000          s/soc/split@14018000          z/soc/split@14019000          /soc/dpi@1401d000            /soc/dsi@1401b000            /soc/dsi@1401c000            /soc/rdma@14001000           /soc/rdma@14002000           /soc/rsz@14003000            /soc/rsz@14004000            /soc/rsz@14005000            /soc/wdma@14006000           /soc/wrot@14007000           /soc/wrot@14008000           /soc/serial@11002000             /soc/serial@11003000             /soc/serial@11004000             /soc/serial@11005000             /soc/mmc@11230000           /soc/mmc@11240000           /soc/mmc@11260000         opp-table-0           operating-points-v2                     	   opp-507000000               84        & x      opp-702000000               )׫        &       opp-1001000000              ;@        &       opp-1105000000              A@        & eh      opp-1209000000              H@        &       opp-1300000000              M|m         &        opp-1508000000              YA         &       opp-1703000000              e        & *         opp-table-1           operating-points-v2                        opp-507000000               84        & `      opp-702000000               )׫        & :      opp-1001000000              ;@        & %      opp-1209000000              H@        & @      opp-1404000000              SW         & ]      opp-1612000000              `+         &       opp-1807000000              k        &       opp-2106000000              }        & *         cpus                         +       cpu-map    cluster0       core0           4         core1           4            cluster1       core0           4         core1           4               cpu@0           8cpu           arm,cortex-a53          D            Hpsci            V           f           u                              cpu intermediate               	                     
                 cpu@1           8cpu           arm,cortex-a53          D           Hpsci            V           f           u                              cpu intermediate               	                     
                 cpu@100         8cpu           arm,cortex-a72          D           Hpsci            V           f           u                              cpu intermediate                                                                 cpu@101         8cpu           arm,cortex-a72          D          Hpsci            V           f           u                              cpu intermediate                                                                 idle-states         psci       cpu-sleep-0           arm,idle-state                                          @        1                          pmu_a53           arm,cortex-a53-pmu          H                 	           S            pmu_a72           arm,cortex-a72-pmu          H                            S            psci          #    arm,psci-1.0 arm,psci-0.2 arm,psci          Osmc         f          r          z        oscillator0           fixed-clock                             clk26m                   oscillator1           fixed-clock                       }         clk32k        oscillator2           fixed-clock                                 cpum_ck       thermal-zones      cpu-thermal                                             trips      trip-point0           `                  ?passive       trip-point1                             ?passive                  cpu_crit0            8                	  ?critical             cooling-maps       map0                                     "         map1                                     "                  reserved-memory                      +            /   vpu_dma_mem_region@b7000000           shared-dma-pool         D            P          6            @                    timer             arm,armv8-timer                   0  H                              
           G      soc                      +             simple-bus           /   clock-controller@10000000             mediatek,mt8173-topckgen            D                                          power-controller@10001000              mediatek,mt8173-infracfg syscon         D                                ^                    power-controller@10003000             mediatek,mt8173-pericfg syscon          D     0                           ^                    syscfg_pctl_a@10005000        %    mediatek,mt8173-pctl-a-syscfg syscon            D     P                         pinctrl@1000b000              mediatek,mt8173-pinctrl         D                     k                                                          $  H                                   %  EC_INT_1V8 SD_CD_L ALC5514_IRQ ALC5650_IRQ AP_FLASH_WP_L SFIN SFCS0 SFHOLD SFOUT SFCK WRAP_EVENT_S_EINT10 PMU_INT I2S2_WS_ALC5650 I2S2_BCK_ALC5650 PWR_BTN_1V8 DA9212_IRQ IDDIG WATCHDOG CEC HDMISCK HDMISD HTPLG MSDC3_DAT0 MSDC3_DAT1 MSDC3_DAT2 MSDC3_DAT3 MSDC3_CLK MSDC3_CMD USB_C0_OC_FLAGB USBA_OC1_L PS8640_1V2_ENABLE THERM_ALERT_N PANEL_LCD_POWER_EN ANX7688_CHIP_PD_C EC_IN_RW_1V8 ANX7688_1V_EN_C USB_DP_HPD_C TPM_DAVINT_N MARVELL8897_IRQ EN_USB_A0_PWR USBA_A0_OC_L EN_PP3300_DX_EDP  SOC_I2C2_1V8_SDA_400K SOC_I2C2_1V8_SCL_400K SOC_I2C0_1V8_SDA_400K SOC_I2C0_1V8_SCL_400K EMMC_ID1 EMMC_ID0 MEM_CONFIG3 EMMC_ID2 MEM_CONFIG1 MEM_CONFIG2 BRD_ID2 MEM_CONFIG0 BRD_ID0 BRD_ID1 EMMC_DAT0 EMMC_DAT1 EMMC_DAT2 EMMC_DAT3 EMMC_DAT4 EMMC_DAT5 EMMC_DAT6 EMMC_DAT7 EMMC_CLK EMMC_CMD EMMC_RCLK PLT_RST_L LID_OPEN_1V8_L AUDIO_SPI_MISO_R  AC_OK_1V8 SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 SD_CLK SD_CMD PWRAP_SPI0_MI PWRAP_SPI0_MO PWRAP_SPI0_CK PWRAP_SPI0_CSN   WIFI_PDN RTC32K_1V8 DISP_PWM0 TOUCHSCREEN_INT_L  SRCLKENA0 SRCLKENA1 PS8640_MODE_CONF TOUCHSCREEN_RESET_R PLATFORM_PROCHOT_L PANEL_POWER_EN REC_MODE_L EC_FW_UPDATE_L ACCEL2_INT_L HDMI_DP_INT ACCELGYRO3_INT_L ACCELGYRO4_INT_L SPI_EC_CLK SPI_EC_MI SPI_EC_MO SPI_EC_CSN SOC_I2C3_1V8_SDA_400K SOC_I2C3_1V8_SCL_400K        PS8640_SYSRSTN_1V8 APIN_MAX98090_DOUT2 TP_INT_1V8_L_R RST_USB_HUB_R BT_WAKE_L ACCEL1_INT_L TABLET_MODE_L  V_UP_IN_L_R V_DOWN_IN_L_R SOC_I2C1_1V8_SDA_1M SOC_I2C1_1V8_SCL_1M PS8640_PDN_1V8 MAX98090_LRCLK MAX98090_BCLK MAX98090_MCLK APOUT_MAX98090_DIN APIN_MAX98090_DOUT SOC_I2C4_1V8_SDA_400K SOC_I2C4_1V8_SCL_400K                  xxx            M   pins1                                        i2c0                  pins1             -  .                  i2c1               '   pins1             }  ~               da9211_pins                              i2c2               (   pins1             +  ,                  i2c3               -   pins1             j  k                  i2c4       pins1                                 i2c6               0   pins1             d  e                  aud_i2s2               c   pins1                                           bl_fixed_pins              X   pins1                        !         bt_wake_pins       pins1             w                   disp_pwm0_pins             K   pins1             W         !         gpio_keys_pins             Y   volume_pins           {   |                tablet_mode_pins              y                   hdmi_mux_pins      pins1             $       pins2             b                   ,         mmc0default            2   pins_cmd_dat          $    9  :  ;  <  =  >  ?  @  B               pins_clk              A               pins_rst              D                  mmc1default            6   pins_cmd_dat              I  J  K  L  N                 8              f      pins_clk              M                 8         pins_insert                           pins_wp           *                            mmc3default            :   pins_dat                                     8              f      pins_cmd                               8              f      pins_clk                               8            mmc0               3   pins_cmd_dat          $    9  :  ;  <  =  >  ?  @  B                 8              e      pins_clk              A        8              e      pins_ds           C        8   
           e      pins_rst              D                  mmc1               7   pins_cmd_dat              I  J  K  L  N                 8              f      pins_clk              M        8              f         mmc3               ;   pins_dat                                     8              f      pins_cmd                               8              f      pins_clk                      8              f         nor            ,   pins1                                  8                  pins2                     8                  pins_clk              	                 8                     panel_backlight_en_pins            W   pins1             _          panel_fixed_pins               ]   pins1             )          ps8640_pins            "   pins1             \   s             ps8640_fixed_pins              ^   pins1                       rt5650_irq             !   pins1                                sdio_fixed_3v3_pins            _   pins1             U          !         spi1               )   pins1                              pins_spi              f  g  h  i                  trackpad_irq               .   pins1             u                            usb            B   pins1             e          ,                  wifi_wake_pins     pins1             &                      syscon@10006000       )    mediatek,mt8173-scpsys syscon simple-mfd            D     `           power-controller          !    mediatek,mt8173-power-controller                         +            G              1   power-domain@0          D                  U        mm          G          power-domain@1          D                 U      X        mm venc         G          power-domain@2          D                 U        mm          G          power-domain@3          D                 U        mm          G            [         power-domain@4          D                 U      i      
  mm venclt           G          power-domain@5          D           G          power-domain@6          D           G          power-domain@7          D                      mfg                      +            G           m      power-domain@8          D                        +            G      power-domain@9          D   	        G            [                     watchdog@10007000         (    mediatek,mt8173-wdt mediatek,mt6589-wdt         D     p              timer@10008000        ,    mediatek,mt8173-timer mediatek,mt6577-timer         D                     H                              x      pwrap@1000d000            mediatek,mt8173-pwrap           D                     {pwrap           H                                pwrap                 
            	  spi wrap       mt6397            mediatek,mt6397                      +                       H                             mt6397clock           mediatek,mt6397-clk                  pinctrl           mediatek,mt6397-pinctrl                                    mt6397regulator           mediatek,mt6397-regulator      buck_vpca15         buck_vpca15         vpca15           
`         p          0                                   
      buck_vpca7          buck_vpca7          vpca7            
`         p          0        -   s               buck_vsramca15          buck_vsramca15        
  vsramca15            
`         p          0               buck_vsramca7           buck_vsramca7         	  vsramca7             
`         p          0                          buck_vcore          buck_vcore          vcore            
`         p          0               buck_vgpu         
  buck_vgpu           vgpu             
`         p          0        -   s      buck_vdrm         
  buck_vdrm           vdrm             O         \          0               buck_vio18          buck_vio18          vio18                      6`          0                    5      ldo_vtcxo         
  ldo_vtcxo           vtcxo                  ldo_va28          	  ldo_va28            va28          ldo_vcama         
  ldo_vcama           vcama            w@         w@        -                     ldo_vio28         
  ldo_vio28           vio28                  ldo_vusb          	  ldo_vusb            vusb               A      ldo_vmc         ldo_vmc         vmc          w@         2Z        -              9      ldo_vmch          	  ldo_vmch            vmch             -         2Z        -              8      ldo_vemc3v3         ldo_vemc3v3       	  vemc_3v3             -         2Z        -              4      ldo_vgp1          	  ldo_vgp1            vcamd            w@         w@        -                    ldo_vgp2          	  ldo_vgp2            vcamio           2Z         2Z        -              $      ldo_vgp3          	  ldo_vgp3            vcamaf           w@         w@        -              =      ldo_vgp4          	  ldo_vgp4            vgp4             O         2Z        -         ldo_vgp5          	  ldo_vgp5            vgp5             O         -        -         ldo_vgp6          	  ldo_vgp6            vgp6             2Z         2Z        -                       /      ldo_vibr          	  ldo_vibr            vibr                       2Z        -            mt6397rtc             mediatek,mt6397-rtc       syscfg_pctl_pmic@c000         (    mediatek,mt6397-pctl-pmic-syscfg syscon         D                         cec@10013000              mediatek,mt8173-cec         D    0                H                        	        Iokay          vpu@10020000              mediatek,mt8173-vpu          D                                  {tcm cfg_reg         H                        g        main            P              F      intpol-controller@10200620        .    mediatek,mt8173-sysirq mediatek,mt6577-sysirq                                           D                               iommu@10205000            mediatek,mt8173-m4u         D     P                H                                bclk            [           ^                          m              E      efuse@10206000            mediatek,mt8173-efuse           D     `                             +      calib@528           D  (              +         clock-controller@10209000             mediatek,mt8173-apmixedsys          D                                         hdmi-phy@10209100             mediatek,mt8173-hdmi-phy            D             $                      pll_ref         hdmitx_dig_cts          z                                              Iokay               N      mailbox@10212000              mediatek,mt8173-gce         D    !                 H                                gce                       C      dsi-phy@10215000              mediatek,mt8173-mipi-tx         D    !P                           mipi_tx0_pll                                    Iokay               G      dsi-phy@10216000              mediatek,mt8173-mipi-tx         D    !`                           mipi_tx1_pll                                  	  Idisabled               I      interrupt-controller@10221000             arm,gic-400                                       @  D    "            "              "@             "`                 H      	                   auxadc@11001000           mediatek,mt8173-auxadc          D                                   main                          *      serial@11002000       *    mediatek,mt8173-uart mediatek,mt6577-uart           D                      H       S                 $            	  baud bus            Iokay          serial@11003000       *    mediatek,mt8173-uart mediatek,mt6577-uart           D     0                H       T                 %            	  baud bus          	  Idisabled          serial@11004000       *    mediatek,mt8173-uart mediatek,mt6577-uart           D     @                H       U                 &            	  baud bus          	  Idisabled          serial@11005000       *    mediatek,mt8173-uart mediatek,mt6577-uart           D     P                H       V                 '            	  baud bus          	  Idisabled          i2c@11007000              mediatek,mt8173-i2c          D     p        p                     H       L                                        	  main dma            default                                 +            Iokay             @   audio-codec@1a            realtek,rt5650          D                                              H              default            !                              '              `      edp-bridge@8              parade,ps8640           D           7                 G      s           default            "        S   #        `   $   ports                        +       port@0          D       endpoint            m   %           H         port@1          D      endpoint            m   &           \                  i2c@11008000              mediatek,mt8173-i2c          D             p                    H       M                                        	  main dma            default            '                     +            Iokay             `   da9211@68             dlg,da9211          D   h                    H         regulators     BUCKA           VBUCKA           
`         0        }          C#          '                                        BUCKB           VBUCKB           
`         0        }          -          '                          i2c@11009000              mediatek,mt8173-i2c          D             p                     H       N                                        	  main dma            default            (                     +            Iokay       tpm@20            infineon,slb9645tt          D                      spi@1100a000              mediatek,mt8173-spi                      +            D                     H       n                 4      \              parent-clk sel-clk spi-clk          Iokay            default            )              ec@0              google,cros-ec-spi          D                                  H                    i2c-tunnel0           google,cros-ec-i2c-tunnel                                    +       sbs-battery@b             sbs,sbs-battery         D                      ,            keyboard-controller           google,cros-ec-keyb         A           Q            d     D  ~  ; < = > ? @ A	 B	 C  D  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i            thermal@1100b000                          mediatek,mt8173-thermal         D                     H       F                               therm auxadc                             *                      +        calibration-data               
                            spi@1100d000              mediatek,mt8173-nor         D                           \                         !      r              spi sf axi                       +            Iokay            default            ,   flash@0           jedec,spi-nor           D                     i2c@11010000              mediatek,mt8173-i2c          D             p                    H       O                                        	  main dma            default            -                     +            Iokay                touchscreen@10            elan,ekth3500           D                       H   X         touchscreen@34            melfas,mip4_ts          D   4                    H   X         touchscreen@20            hid-over-i2c            D            #                        H   X            i2c@11011000              mediatek,mt8173-i2c          D            p                     H       P                                        	  main dma            default            .                     +            Iokay                trackpad@15           elan,ekth3000                       H   u           D           2   /         =      trackpad@2c           hid-over-i2c                        H   u           D   ,        #             =         i2c@11012000              mediatek,mt8173-hdmi-ddc            H       Q           D                                   ddc-i2c            d      i2c@11013000              mediatek,mt8173-i2c          D    0        p                     H       R                            #            	  main dma            default            0                     +          	  Idisabled          audio-controller@11220000             mediatek,mt8173-afe-pcm         D    "                 H                  K   1         P              d      e      y                                          b  infra_sys_audio_clk top_pdn_audio top_pdn_aud_intbus bck0 bck1 i2s0_m i2s1_m i2s2_m i2s3_m i2s3_b                 m      n                               b      mmc@11230000              mediatek,mt8173-mmc         D    #                 H       G                       _        source hclk         Iokay            default state_uhs              2        Y   3        c                     m                                    @                                       	   4        	&   5              `              &         	3      mmc@11240000              mediatek,mt8173-mmc         D    $                 H       H                       R        source hclk         Iokay            default state_uhs              6        Y   7        c                     	A         	R         	_        	m                 	   8        	&   9        	v      *          mmc@11250000              mediatek,mt8173-mmc         D    %                 H       I                       R        source hclk       	  Idisabled          mmc@11260000              mediatek,mt8173-mmc         D    &                 H       J                       u        source hclk         Iokay            default state_uhs              :        Y   ;        c                     	A         	R         	_         	         =         	        	   <        	&   =         	3         	                     +       btmrvl@2              marvell,sd8897-bt           D                       H   w           	           	 d        mwifiex@1             marvell,sd8897          D                       H   &           	            usb@11271000          #    mediatek,mt8173-mtu3 mediatek,mtu3           D    '       0     (              	  {mac ippc            H       @           	   >      ?      @           K   1                 ^           sys_ck ref_ck           	                              +            /        Iokay            	host             =        
   A   usb@11270000          '    mediatek,mt8173-xhci mediatek,mtk-xhci          D    '                 {mac         H       s           K   1                 ^           sys_ck ref_ck           Iokay            default            B        
   A         t-phy@11290000            mediatek,mt8173-u3phy           D    )                              +            /        Iokay       usb-phy@11290800            D    )                              ref                    Iokay               >      usb-phy@11290900            D    )	                           ref                    Iokay               ?      usb-phy@11291000            D    )                              ref                    Iokay               @         syscon@14000000           mediatek,mt8173-mmsys syscon            D                      K   1                 U        
ׄ                    ^           
%   C          C              
,   C                     D      rdma@14001000         -    mediatek,mt8173-mdp-rdma mediatek,mt8173-mdp            D                        D      D           K   1           
D   E           
K   F      rdma@14002000             mediatek,mt8173-mdp-rdma            D                         D      D           K   1           
D   E         rsz@14003000              mediatek,mt8173-mdp-rsz         D     0                   D           K   1         rsz@14004000              mediatek,mt8173-mdp-rsz         D     @                   D           K   1         rsz@14005000              mediatek,mt8173-mdp-rsz         D     P                   D           K   1         wdma@14006000             mediatek,mt8173-mdp-wdma            D     `                   D           K   1           
D   E         wrot@14007000             mediatek,mt8173-mdp-wrot            D     p                   D           K   1           
D   E         wrot@14008000             mediatek,mt8173-mdp-wrot            D                        D           K   1           
D   E         ovl@1400c000              mediatek,mt8173-disp-ovl            D                     H                  K   1              D           
D   E            
,   C               ovl@1400d000              mediatek,mt8173-disp-ovl            D                     H                  K   1              D           
D   E           
,   C               rdma@1400e000             mediatek,mt8173-disp-rdma           D                     H                  K   1              D           
D   E           
,   C               rdma@1400f000             mediatek,mt8173-disp-rdma           D                     H                  K   1              D           
D   E           
,   C               rdma@14010000             mediatek,mt8173-disp-rdma           D                     H                  K   1              D           
D   E           
,   C                wdma@14011000             mediatek,mt8173-disp-wdma           D                    H                  K   1              D           
D   E           
,   C               wdma@14012000             mediatek,mt8173-disp-wdma           D                     H                  K   1              D           
D   E           
,   C                color@14013000            mediatek,mt8173-disp-color          D    0                H                  K   1              D           
,   C     0          color@14014000            mediatek,mt8173-disp-color          D    @                H                  K   1              D           
,   C     @          aal@14015000              mediatek,mt8173-disp-aal            D    P                H                  K   1              D           
,   C     P          gamma@14016000            mediatek,mt8173-disp-gamma          D    `                H                  K   1              D           
,   C     `          merge@14017000            mediatek,mt8173-disp-merge          D    p                K   1              D         split@14018000            mediatek,mt8173-disp-split          D                    K   1              D         split@14019000            mediatek,mt8173-disp-split          D                    K   1              D         ufoe@1401a000             mediatek,mt8173-disp-ufoe           D                    H                  K   1              D           
,   C               dsi@1401b000              mediatek,mt8173-dsi         D                    H                  K   1              D   $   D   %   G        engine digital hs              D           	   G        
Xdphy            Iokay       ports      port       endpoint            m   H           %               dsi@1401c000              mediatek,mt8173-dsi         D                    H                  K   1              D   &   D   '   I        engine digital hs           	   I        
Xdphy          	  Idisabled          dpi@1401d000              mediatek,mt8173-dpi         D                    H                  K   1              D   (   D   )              pixel engine pll            Iokay       port       endpoint            m   J           O            pwm@1401e000          2    mediatek,mt8173-disp-pwm mediatek,mt6595-disp-pwm           D                    
b              D   !   D            main mm         Iokay            default            K           U      pwm@1401f000          2    mediatek,mt8173-disp-pwm mediatek,mt6595-disp-pwm           D                    
b              D   #   D   "        main mm       	  Idisabled          mutex@14020000            mediatek,mt8173-disp-mutex          D                     H                  K   1              D           
,   C                  
m   5   6      larb@14021000             mediatek,mt8173-smi-larb            D                    
   L        K   1              D      D           apb smi                  smi@14022000              mediatek,mt8173-smi-common          D                     K   1              D      D           apb smi            L      od@14023000           mediatek,mt8173-disp-od         D    0                   D           
,   C     0          hdmi@14025000             mediatek,mt8173-hdmi            D    P                H                      D   ,   D   -   D   .   D   /        pixel pll bclk spdif            default            M        	   N        
Xhdmi            
   D  	               s           N        Iokay               a   ports                        +       port@0          D       endpoint            m   O           J         port@1          D      endpoint            m   P           e               larb@14027000             mediatek,mt8173-smi-larb            D    p                
   L        K   1              D   2   D   2        apb smi                  clock-controller@15000000             mediatek,mt8173-imgsys syscon           D                                    Q      larb@15001000             mediatek,mt8173-smi-larb            D                     
   L        K   1              Q      Q           apb smi                  clock-controller@16000000             mediatek,mt8173-vdecsys syscon          D                                    R      vcodec@16000000           mediatek,mt8173-vcodec-dec          D                                                                    0            @            P            h            p            x                            H                @  
D   E       E   !   E   %   E   &   E   '   E   "   E   #   E   $        
K   F        K   1          @        
      >      l      W      M            i      N      Z  vcodecpll univpll_d2 clk_cci400_sel vdec_sel vdecpll vencpll venc_lt_sel vdec_bus_clk_src         (        i      l      W      
                    N      >      M        
            XU/       larb@16010000             mediatek,mt8173-smi-larb            D                     
   L        K   1               R      R           apb smi                  clock-controller@18000000             mediatek,mt8173-vencsys syscon          D                                    S      larb@18001000             mediatek,mt8173-smi-larb            D                     
   L        K   1              S      S           apb smi                  vcodec@18002000           mediatek,mt8173-vcodec-enc          D                      H                X  
D   E   `   E   a   E   b   E   c   E   d   E   i   E   j   E   k   E   l   E   m   E   n        
K   F              X      	  venc_sel                  X              M        K   1         jpegdec@18004000              mediatek,mt8173-jpgdec          D     @                H                     S      S           jpgdec-smi jpgdec           K   1           
D   E   g   E   h      clock-controller@19000000         !    mediatek,mt8173-vencltsys syscon            D                                    T      larb@19001000             mediatek,mt8173-smi-larb            D                     
   L        K   1              T      T           apb smi                  vcodec@19002000           mediatek,mt8173-vcodec-enc-vp8          D                      H                H  
D   E      E      E      E      E      E      E      E      E           
K   F              i        venc_lt_sel               i              N        K   1            memory@40000000         8memory          D    @                backlight             pwm-backlight           
   U     B@        
   V        
      _            default            W        Iokay               [      fixedregulator2           regulator-fixed       	  bl_fixed             w@         w@        
           
        
                   default            X           V      chosen          
serial0:115200n8          gpio-keys         
    gpio-keys           default            Y   switch-lid          
Lid         A      E           
                              switch-power            
Power           A                  
   t        )                  switch-tablet-mode          
Tablet_mode         A      y            
                             switch-volume-down          
Volume_down         A      {           
   r      switch-volume-up          
  
Volume_up           A      |           
   s         panel             lg,lp120up1         
   Z        ;   [   port       endpoint            m   \           &            regulator1            regulator-fixed       
  PANEL_3V3            2Z         2Z         
        
      )            default            ]           Z      regulator2            regulator-fixed         PS8640_1V2           O         O        -           
         E        
                  default            ^           #      fixedregulator0           regulator-fixed         3V3          2Z         2Z        
      U            default            _           <      sound             mediatek,mt8173-rt5650          W   `   a        l   b        default            c        ~      codec-capture              `            connector             hdmi-connector          
hdmi            ?a              d   port       endpoint            m   e           P               	compatible interrupt-parent #address-cells #size-cells model ovl0 ovl1 rdma0 rdma1 rdma2 wdma0 wdma1 color0 color1 split0 split1 dpi0 dsi0 dsi1 mdp-rdma0 mdp-rdma1 mdp-rsz0 mdp-rsz1 mdp-rsz2 mdp-wdma0 mdp-wrot0 mdp-wrot1 serial0 serial1 serial2 serial3 mmc0 mmc1 mmc2 opp-shared phandle opp-hz opp-microvolt cpu device_type reg enable-method cpu-idle-states #cooling-cells dynamic-power-coefficient clocks clock-names operating-points-v2 capacity-dmips-mhz proc-supply sram-supply entry-method local-timer-stop entry-latency-us exit-latency-us min-residency-us arm,psci-suspend-param interrupts interrupt-affinity cpu_suspend cpu_off cpu_on #clock-cells clock-frequency clock-output-names polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution ranges alignment no-map arm,no-tick-in-suspend #reset-cells mediatek,pctl-regmap pins-are-numbered gpio-controller #gpio-cells interrupt-controller #interrupt-cells gpio-line-names pinmux input-enable bias-pull-down bias-disable bias-pull-up output-low output-high drive-strength #power-domain-cells mediatek,infracfg domain-supply reg-names resets reset-names regulator-compatible regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-always-on regulator-allowed-modes regulator-enable-ramp-delay status memory-region mediatek,larbs #iommu-cells mediatek,ibias mediatek,ibias_up #phy-cells #mbox-cells #io-channel-cells clock-div pinctrl-names pinctrl-0 avdd-supply cpvdd-supply #sound-dai-cells realtek,dmic1-data-pin realtek,jd-mode powerdown-gpios reset-gpios vdd12-supply vdd33-supply remote-endpoint regulator-min-microamp regulator-max-microamp powered-while-suspended mediatek,pad-select spi-max-frequency google,cros-ec-spi-msg-delay google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap #thermal-sensor-cells mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names bank0-supply bank1-supply assigned-clocks assigned-clock-parents hid-descr-addr vcc-supply wakeup-source power-domains pinctrl-1 bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset hs400-ds-delay mediatek,hs200-cmd-int-delay mediatek,hs400-cmd-int-delay mediatek,hs400-cmd-resp-sel-rising vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 cd-gpios wp-gpios keep-power-in-suspend cap-sdio-irq cap-power-off-card marvell,wakeup-pin marvell,wakeup-gap-ms phys mediatek,syscon-wakeup dr_mode vusb33-supply assigned-clock-rates mboxes mediatek,gce-client-reg iommus mediatek,vpu phy-names #pwm-cells mediatek,gce-events mediatek,smi mediatek,syscon-hdmi pwms power-supply enable-gpios startup-delay-us enable-active-high gpio stdout-path label linux,code linux,input-type gpio-key,wakeup debounce-interval backlight regulator-boot-on mediatek,audio-codec mediatek,platform mediatek,mclk sound-dai ddc-i2c-bus 