  2>   8  0   (            &  /                                                                      ,Spreadtrum SP9863A-1H10 Board            2sprd,sp9863a-1h10 sprd,sc9863a     soc          2simple-bus                                     =   syscon@20e00000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D             @                                   =             @    apahb-gate           2sprd,sc9863a-apahb-gate          D                H            U   +         syscon@402b0000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D    @+        @                                   =        @+    @    pmu-gate             2sprd,sc9863a-pmu-gate            D                ]            dext-26m          H            syscon@402e0000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D    @.        @                                   =        @.    @    aonapb-gate          2sprd,sc9863a-aonapb-gate             D                H            syscon@40353000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D    @50       0                                   =        @50   0    pll          2sprd,sc9863a-pll             D                ]            dext-26m          H            syscon@40359000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D    @5       0                                   =        @5   0    mpll             2sprd,sc9863a-mpll            D                H            syscon@4035c000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D    @5       0                                   =        @5   0    rpll             2sprd,sc9863a-rpll            D                ]            dext-26m          H            U   ,         syscon@40363000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D    @60       0                                   =        @60   0    dpll             2sprd,sc9863a-dpll            D                H            syscon@60800000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D    `                                           =        `    0    mm-gate          2sprd,sc9863a-mm-gate             D                H            syscon@71300000       '   2sprd,sc9863a-glbregs syscon simple-mfd           D    q0        @                                   =        q0    @    apapb-gate           2sprd,sc9863a-apapb-gate          D                ]            dext-26m          H            apb@70000000             2simple-bus                                    =        p         serial@0          #   2sprd,sc9863a-uart sprd,sc9836-uart           D                p                   ]            {okay          serial@100000         #   2sprd,sc9863a-uart sprd,sc9836-uart           D               p                   ]            {okay          serial@200000         #   2sprd,sc9863a-uart sprd,sc9836-uart           D                p                   ]         	   {disabled          serial@300000         #   2sprd,sc9863a-uart sprd,sc9836-uart           D 0              p                   ]         	   {disabled          serial@400000         #   2sprd,sc9863a-uart sprd,sc9836-uart           D @              p                   ]         	   {disabled             interrupt-controller@14000000            2arm,gic-v3                                                 =                                                D                                    p      	            U         clock-controller@21500000            2sprd,sc9863a-ap-clk          D    !P                  ]               dext-32k ext-26m          H         clock-controller@402d0000            2sprd,sc9863a-aon-clk             D    @-                  ]                      dext-26m rco-100m ext-32k ext-4m          H            U   *      clock-controller@60900000            2sprd,sc9863a-mm-clk          D    `                  H         funnel@10001000       +   2arm,coresight-dynamic-funnel arm,primecell           D                      ]         	   dapb_pclk       out-ports      port       endpoint                         U               in-ports       port       endpoint                         U                  etb@10003000              2arm,coresight-tmc arm,primecell          D     0                 ]         	   dapb_pclk       in-ports       port       endpoint                         U                  funnel@12001000       +   2arm,coresight-dynamic-funnel arm,primecell           D                      ]         	   dapb_pclk       out-ports      port       endpoint                	         U               in-ports                                 port@0           D       endpoint                
         U            port@1           D      endpoint                         U            port@2           D      endpoint                         U            port@3           D      endpoint                         U   !               etf@12002000              2arm,coresight-tmc arm,primecell          D                       ]         	   dapb_pclk       out-ports      port       endpoint                         U               in-port    port       endpoint                         U   	               etf@12003000              2arm,coresight-tmc arm,primecell          D     0                 ]         	   dapb_pclk       out-ports      port       endpoint                         U               in-ports       port       endpoint                         U                  funnel@12004000       +   2arm,coresight-dynamic-funnel arm,primecell           D     @                 ]         	   dapb_pclk       out-ports      port       endpoint                         U               in-ports                                 port@0           D       endpoint                         U            port@1           D      endpoint                         U                  funnel@12005000       +   2arm,coresight-dynamic-funnel arm,primecell           D     P                 ]         	   dapb_pclk       out-ports      port       endpoint                         U               in-ports                                 port@0           D       endpoint                         U   #         port@1           D      endpoint                         U   %         port@2           D      endpoint                         U   '         port@3           D      endpoint                         U   )               etm@13040000          "   2arm,coresight-etm4x arm,primecell            D                                  ]         	   dapb_pclk       out-ports      port       endpoint                         U   
               etm@13140000          "   2arm,coresight-etm4x arm,primecell            D                                  ]         	   dapb_pclk       out-ports      port       endpoint                         U                  etm@13240000          "   2arm,coresight-etm4x arm,primecell            D    $                              ]         	   dapb_pclk       out-ports      port       endpoint                         U                  etm@13340000          "   2arm,coresight-etm4x arm,primecell            D    4                               ]         	   dapb_pclk       out-ports      port       endpoint                !         U                  etm@13440000          "   2arm,coresight-etm4x arm,primecell            D    D                     "         ]         	   dapb_pclk       out-ports      port       endpoint                #         U                  etm@13540000          "   2arm,coresight-etm4x arm,primecell            D    T                     $         ]         	   dapb_pclk       out-ports      port       endpoint                %         U                  etm@13640000          "   2arm,coresight-etm4x arm,primecell            D    d                     &         ]         	   dapb_pclk       out-ports      port       endpoint                '         U                  etm@13740000          "   2arm,coresight-etm4x arm,primecell            D    t                     (         ]         	   dapb_pclk       out-ports      port       endpoint                )         U                  ap-ahb           2simple-bus                                     =   sdio@20300000            2sprd,sdhci-r11           D     0                  p       9            dsdio enable          ]   *      +               *               ,                                !      sdio@20600000            2sprd,sdhci-r11           D     `                  p       <            dsdio enable          ]   *   !   +               *   !            ,                       (                  6         <            ext-26m          2fixed-clock          H            M        ]ext-26m          U         ext-32k          2fixed-clock          H            M           ]ext-32k          U         ext-4m           2fixed-clock          H            M =	         ]ext-4m           U         rco-100m             2fixed-clock          H            M       	  ]rco-100m             U         cpus                                 cpu-map    cluster0       core0                     core1                     core2                     core3                      core4               "      core5               $      core6               &      core7               (            cpu@0           pcpu          2arm,cortex-a55           D                |psci               -         U         cpu@100         pcpu          2arm,cortex-a55           D               |psci               -         U         cpu@200         pcpu          2arm,cortex-a55           D               |psci               -         U         cpu@300         pcpu          2arm,cortex-a55           D               |psci               -         U          cpu@400         pcpu          2arm,cortex-a55           D               |psci               -         U   "      cpu@500         pcpu          2arm,cortex-a55           D               |psci               -         U   $      cpu@600         pcpu          2arm,cortex-a55           D               |psci               -         U   &      cpu@700         pcpu          2arm,cortex-a55           D               |psci               -         U   (         idle-states         psci       core-pd          2arm,idle-state                                '                             U   -         psci             2arm,psci-0.2            smc       timer            2arm,armv8-timer       0   p                                 
         pmu          2arm,armv8-pmuv3       `   p                                                                                      aliases         /soc/apb@70000000/serial@0           	/soc/apb@70000000/serial@100000       memory@80000000         pmemory           D                    chosen          serial1:115200n8          	  earlycon             	interrupt-parent #address-cells #size-cells model compatible ranges reg #clock-cells phandle clocks clock-names interrupts status #interrupt-cells redistributor-stride #redistributor-regions interrupt-controller remote-endpoint cpu assigned-clocks assigned-clock-parents bus-width no-sdio no-mmc non-removable no-sd cap-mmc-hw-reset clock-frequency clock-output-names device_type enable-method cpu-idle-states entry-method entry-latency-us exit-latency-us min-residency-us local-timer-stop arm,psci-suspend-param serial0 serial1 stdout-path bootargs 