  k   8     (                                           $    mediatek,mt8192-evb mediatek,mt8192                                  +         !   7MediaTek MT8192 evaluation board       aliases          =/soc/ovl@14005000            B/soc/ovl@14006000            J/soc/ovl@14014000            R/soc/rdma@14007000           X/soc/rdma@14015000           ^/soc/serial@11002000          fixed-factor-clock-13m            fixed-factor-clock           f             s            z                        clk13m              #      oscillator0           fixed-clock          f                      clk26m                    oscillator1           fixed-clock          f                         clk32k        cpus                         +       cpu@0            cpu           arm,cortex-a55                        psci             ec3@                                                  	      cpu@100          cpu           arm,cortex-a55                       psci             ec3@                                                  
      cpu@200          cpu           arm,cortex-a55                       psci             ec3@                                                        cpu@300          cpu           arm,cortex-a55                       psci             ec3@                                                        cpu@400          cpu           arm,cortex-a76                       psci             f                                                         cpu@500          cpu           arm,cortex-a76                       psci             f                                                         cpu@600          cpu           arm,cortex-a76                       psci             f                                                         cpu@700          cpu           arm,cortex-a76                       psci             f                                                         cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          l2-cache0             cache                                 l2-cache1             cache                                 l3-cache              cache                     idle-states         psci       cpu-sleep-l           arm,idle-state                     4        E   7        V           f                    cpu-sleep-b           arm,idle-state                     4        E   #        V           f                    cluster-sleep-l           arm,idle-state                    4        E   <        V           f  \                  cluster-sleep-b           arm,idle-state                    4        E   (        V           f                          pmu-a55           arm,cortex-a55-pmu                      w                  pmu-a76           arm,cortex-a76-pmu                      w                  psci              arm,psci-1.0             smc       timer             arm,armv8-timer                   @  w                                             
                 ]@      soc                      +             simple-bus              interrupt-controller@c000000              arm,gic-v3                                                                                           w      	                      ppi-partitions     interrupt-partition-0              	   
                        interrupt-partition-1                                               syscon@10000000            mediatek,mt8192-topckgen syscon                                 f                     syscon@10001000            mediatek,mt8192-infracfg syscon                                f                                syscon@10003000           mediatek,mt8192-pericfg syscon                0                 f               '      pinctrl@10005000              mediatek,mt8192-pinctrl               P                                                                                                                                                ]  iocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint                                                               w                                           syscon@10006000       )    mediatek,mt8192-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8192-power-controller                         +                           )   power-domain@0                        s            :      /        "audio audio1 audio2         .                     power-domain@1                       s              "conn            .                     power-domain@2                       s              "mfg                      +                  power-domain@3                      .                        +                  power-domain@4                                power-domain@5                                power-domain@6                                power-domain@7                                power-domain@8                                      power-domain@9              	      (   s                                    !  "disp disp-0 disp-1 disp-2 disp-3            .                        +                  power-domain@10             
      (   s                                       "ipe ipe-0 ipe-1 ipe-2 ipe-3         .                     power-domain@11                      s                           "isp isp-0 isp-1         .                     power-domain@12                      s                           "isp2 isp2-0 isp2-1          .                     power-domain@13                      s                  
  "mdp mdp-0           .                     power-domain@14                      s      3              "venc venc-0         .                     power-domain@15                       s      4                           "vdec vdec-0 vdec-1 vdec-2           .                        +                  power-domain@16                      s                           "vdec2-0 vdec2-1 vdec2-2                      power-domain@17                   (   s      
                                 "cam cam-0 cam-1 cam-2 cam-3         .                        +                  power-domain@18                      s                "cam_rawa-0                    power-domain@19                      s   !            "cam_rawb-0                    power-domain@20                      s   "            "cam_rawc-0                                watchdog@10007000             mediatek,mt8192-wdt               p                               (      syscon@1000c000       "    mediatek,mt8192-apmixedsys syscon                                  f               &      timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer              p                w                       s   #      pwrap@10026000            mediatek,mt6873-pwrap                `                pwrap           w                       s                   	  "spi wrap            @              P         pmic              mediatek,mt6359                        mt6359codec       regulators     buck_vs1            gvs1         v 5          !                           buck_vgpu11         gvgpu11          v          7                                             buck_vmodem         gvmodem          v                    *                 buck_vpu            gvpu         v          7                                             buck_vcore          gvcore           v                                                        buck_vs2            gvs2         v 5          j                            buck_vpa            gvpa         v           7          ,      buck_vproc2         gvproc2          v          7          L                                   buck_vproc1         gvproc1          v          7          L                                   buck_vcore_sshub            gvcore_sshub         v          7      buck_vgpu11_sshub           gvgpu11_sshub            v          7      ldo_vaud18          gvaud18          v w@         w@                 ldo_vsim1           gvsim1           v          /M`      ldo_vibr            gvibr            v O         2Z      ldo_vrf12           gvrf12           v                 ldo_vusb            gvusb            v -         -                         ldo_vsram_proc2         gvsram_proc2         v                     L                          ldo_vio18           gvio18           v                                   ldo_vcamio          gvcamio          v                ldo_vcn18           gvcn18           v w@         w@                 ldo_vfe28           gvfe28           v *         *           x      ldo_vcn13           gvcn13           v                 ldo_vcn33_1_bt          gvcn33_1_bt          v *         5g      ldo_vcn33_1_wifi            gvcn33_1_wifi            v *         5g      ldo_vaux18          gvaux18          v w@         w@                          ldo_vsram_others            gvsram_others            v                                      ldo_vefuse          gvefuse          v                ldo_vxo22           gvxo22           v w@         !               ldo_vrfck           gvrfck           v `               ldo_vrfck_1         gvrfck           v          j       ldo_vbif28          gvbif28          v *         *                 ldo_vio28           gvio28           v *         2Z               ldo_vemc            gvemc            v ,@          2Z      ldo_vemc_1          gvemc            v &%         2Z      ldo_vcn33_2_bt          gvcn33_2_bt          v *         5g      ldo_vcn33_2_wifi            gvcn33_2_wifi            v *         5g      ldo_va12            gva12            v O                         ldo_va09            gva09            v 5          O      ldo_vrf18           gvrf18           v          P      ldo_vsram_md          	  gvsram_md            v                     *                 ldo_vufs            gvufs            v                ldo_vm18            gvm18            v                         ldo_vbbck           gvbbck           v          O      ldo_vsram_proc1         gvsram_proc1         v                     L                          ldo_vsim2           gvsim2           v          /M`      ldo_vsram_others_sshub          gvsram_others_sshub          v                    mt6359rtc             mediatek,mt6358-rtc             spmi@10027000             mediatek,mt6873-spmi                  p                            pmif spmimst             s                   8      (  "pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         @              P            mailbox@10228000              mediatek,mt8192-gce              "       @         w                                  s              "gce             2      clock-controller@10720000             mediatek,mt8192-scp_adsp                 r                  f           fail          serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart                                  w       m                s               	  "baud bus            okay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart                 0                w       n                s               	  "baud bus          	  disabled          clock-controller@11007000             mediatek,mt8192-imp_iic_wrap_c                p                 f         spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  w                       s      M                    "parent-clk sel-clk spi-clk        	  disabled          pwm@1100e000              mediatek,mt8183-disp-pwm                                  w                                  s      !      8        "main mm       	  disabled          spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  w                       s      M            <        "parent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  w                       s      M            >        "parent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                 0                w                       s      M            ?        "parent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 w                       s      M            L        "parent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 w                       s      M            M        "parent-clk sel-clk spi-clk        	  disabled          spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 w                       s      M            m        "parent-clk sel-clk spi-clk        	  disabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 w                       s      M            n        "parent-clk sel-clk spi-clk        	  disabled          scp@10500000              mediatek,mt8192-scp       0       P             r             p                 sram cfg l1tcm          w                      s              "main          	  disabled                E      usb@11200000          '    mediatek,mt8192-xhci mediatek,mtk-xhci                               >              	  mac ippc            !          a               5host            E   $      %           @      "      #        P      ]      ]          s      7   &               R      $  "sys_ck ref_ck mcu_ck dma_ck xhci_ck          J        X   '      f      	  disabled          syscon@11210000           mediatek,mt8192-audsys syscon                !                   f               *   mt8192-afe-pcm            mediatek,mt8192-audio           w                      o   (         	  vaudiosys               &        .                         )            s   *       *      *      *      *      *      *      *      *      *      *   	   *   
   *      *      *      *      *      *      *      *         /      :                  H      /      e      0      i      +      g      ,      k      ;      <      =      >      ?      @      A      B      C      D                                                                        7        u  "aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adda6_adc_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_tdm_clk aud_tml_clk aud_nle aud_dac_hires_clk aud_adc_hires_clk aud_adc_hires_tml aud_adda6_adc_hires_clk aud_3rd_dac_clk aud_3rd_dac_predis_clk aud_3rd_dac_tml aud_3rd_dac_hires_clk aud_infra_clk aud_infra_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d4_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d4 top_mux_aud_eng2 top_apll2_d4 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_i2s6_m_sel top_i2s7_m_sel top_i2s8_m_sel top_i2s9_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_apll12_div5 top_apll12_div6 top_apll12_div7 top_apll12_div8 top_apll12_div9 top_mux_audio_h top_clk26m_clk             pcie@11230000             mediatek,mt8192-pcie             pci              #                	  pcie-mac                         +         0   s      +      '      *      j      ^      \      /  "pl_250m tl_26m tl_96m tl_32k peri_26m top_133m          @      )        P      Q        w                                   8                                                                                        `                    +                      +                     +                     +      interrupt-controller                                                 +         spi@11234000              mediatek,mt8192-nor              #@                w                      s      :      w      ]        "spi sf axi          @      :        P                        +          	  disabled          efuse@11c10000        %    mediatek,mt8192-efuse mediatek,efuse                                               +      data1@1c0                 X      calib@580                 h         i2c@11cb0000              mediatek,mt8192-i2c                            !s                w       s                s   ,          x      	  "main dma             z                        +          	  disabled          clock-controller@11cb1000             mediatek,mt8192-imp_iic_wrap_e                                f               ,      i2c@11d00000              mediatek,mt8192-i2c                            !v               w       w                s   -          x      	  "main dma             z                        +          	  disabled          i2c@11d01000              mediatek,mt8192-i2c                           !w              w       x                s   -         x      	  "main dma             z                        +          	  disabled          i2c@11d02000              mediatek,mt8192-i2c                            !y               w       y                s   -         x      	  "main dma             z                        +          	  disabled          clock-controller@11d03000             mediatek,mt8192-imp_iic_wrap_s               0                 f               -      i2c@11d20000              mediatek,mt8192-i2c                            !q                w       q                s   .          x      	  "main dma             z                        +          	  disabled          i2c@11d21000              mediatek,mt8192-i2c                           !q              w       r                s   .         x      	  "main dma             z                        +          	  disabled          i2c@11d22000              mediatek,mt8192-i2c                            !s              w       t                s   .         x      	  "main dma             z                        +          	  disabled          clock-controller@11d23000              mediatek,mt8192-imp_iic_wrap_ws              0                 f               .      i2c@11e00000              mediatek,mt8192-i2c                            !u                w       u                s   /          x      	  "main dma             z                        +          	  disabled          clock-controller@11e01000             mediatek,mt8192-imp_iic_wrap_w                                f               /      t-phy@11e40000        .    mediatek,mt8192-tphy mediatek,generic-tphy-v2                        +                           usb-phy@0                            s           "ref                        $      usb-phy@700               	          s           "ref                        %         dsi-phy@11e50000              mediatek,mt8183-mipi-tx                                s   &   
         f                         mipi_tx0_pll          	  disabled                5      i2c@11f00000              mediatek,mt8192-i2c                            !p               w       p                s   0          x      	  "main dma             z                        +          	  disabled          i2c@11f01000              mediatek,mt8192-i2c                           !u               w       v                s   0         x      	  "main dma             z                        +          	  disabled          clock-controller@11f02000             mediatek,mt8192-imp_iic_wrap_n                                 f               0      clock-controller@11f10000             mediatek,mt8192-msdc_top                                   f               1      mmc@11f60000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                             w       c             8   s         1   	   1      1      1      1      1         3  "source hclk source_cg sys_cg pclk_cg axi_cg ahb_cg        	  disabled          mmc@11f70000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc                                             w       g             8   s         1   
   1      1      1      1      1         3  "source hclk source_cg sys_cg pclk_cg axi_cg ahb_cg        	  disabled          clock-controller@13fbf000             mediatek,mt8192-mfgcfg                                f         syscon@14000000           mediatek,mt8192-mmsys syscon                                    f                         2          2                 2                            mutex@14001000            mediatek,mt8192-disp-mutex                                w                       s                              )   	      smi@14002000              mediatek,mt8192-smi-common                                   s                                "apb smi gals0 gals1            )   	            3      larb@14003000             mediatek,mt8192-smi-larb                  0                            0   3         s              "apb smi            )   	            6      larb@14004000             mediatek,mt8192-smi-larb                  @                           0   3         s              "apb smi            )   	            7      ovl@14005000              mediatek,mt8192-disp-ovl                  P                w                       s              =   4      4              )   	           2     P          ovl@14006000              mediatek,mt8192-disp-ovl-2l               `                w                         )   	         s              =   4   "   4               2     `          rdma@14007000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma               p                w                       s              =   4           D              )   	           2     p          color@14009000        6    mediatek,mt8192-disp-color mediatek,mt8173-disp-color                                 w                        )   	         s                 2               ccorr@1400a000            mediatek,mt8192-disp-ccorr                                w                        )   	         s      	           2               aal@1400b000          2    mediatek,mt8192-disp-aal mediatek,mt8183-disp-aal                                 w                        )   	         s                 2               gamma@1400c000        6    mediatek,mt8192-disp-gamma mediatek,mt8183-disp-gamma                                 w                        )   	         s                 2               postmask@1400d000             mediatek,mt8192-disp-postmask                                 w                        )   	         s                 2               dither@1400e000       8    mediatek,mt8192-disp-dither mediatek,mt8183-disp-dither                               w                        )   	         s      
           2               dsi@14010000              mediatek,mt8183-dsi                               w      	                s                5        "engine digital hs           E   5        \dphy               )   	        o            	  disabled       port       endpoint                ovl@14014000              mediatek,mt8192-disp-ovl-2l              @                w                        )   	         s              =   4   #   4   !           2     @          rdma@14015000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma              P                w                        )   	         s              =   4   %        D              2     P          dpi@14016000              mediatek,mt8192-dpi              `                w                      s      !         &           "pixel engine pll          	  disabled          m4u@1401d000              mediatek,mt8192-m4u                            <  f   6   7   8   9   :   ;   <   =   >   ?   @   A   B   C   D        w                      s              "bclk               )   	        u               4      clock-controller@15020000             mediatek,mt8192-imgsys                                 f                     larb@1502e000             mediatek,mt8192-smi-larb                                    	        0   3         s                      "apb smi            )               <      clock-controller@15820000             mediatek,mt8192-imgsys2                                f                     larb@1582e000             mediatek,mt8192-smi-larb                                            0   3         s                      "apb smi            )               =      larb@1600d000             mediatek,mt8192-smi-larb                                             0   3         s                      "apb smi            )               :      clock-controller@1600f000             mediatek,mt8192-vdecsys_soc                                f                     larb@1602e000             mediatek,mt8192-smi-larb                                            0   3         s                      "apb smi            )               9      clock-controller@1602f000             mediatek,mt8192-vdecsys                               f                     clock-controller@17000000             mediatek,mt8192-vencsys                                 f                     larb@17010000             mediatek,mt8192-smi-larb                                             0   3         s                     "apb smi            )               ;      vcodec@17020000           mediatek,mt8192-vcodec-enc                               X  =   4      4      4      4      4      4      4      4      4      4      4           w      5                  E           )            s            
  "venc-set1           @      3        P      W      clock-controller@1a000000             mediatek,mt8192-camsys                                  f                     larb@1a001000             mediatek,mt8192-smi-larb                                             0   3         s                     "apb smi            )               >      larb@1a002000             mediatek,mt8192-smi-larb                                              0   3         s                    "apb smi            )               ?      larb@1a00f000             mediatek,mt8192-smi-larb                                             0   3         s                       "apb smi            )               @      larb@1a010000             mediatek,mt8192-smi-larb                                             0   3         s   !      !            "apb smi            )               A      larb@1a011000             mediatek,mt8192-smi-larb                                            0   3         s   "       "           "apb smi            )               B      clock-controller@1a04f000             mediatek,mt8192-camsys_rawa                               f                      clock-controller@1a06f000             mediatek,mt8192-camsys_rawb                               f               !      clock-controller@1a08f000             mediatek,mt8192-camsys_rawc                               f               "      clock-controller@1b000000             mediatek,mt8192-ipesys                                  f                     larb@1b00f000             mediatek,mt8192-smi-larb                                             0   3         s                    "apb smi            )   
            D      larb@1b10f000             mediatek,mt8192-smi-larb                                            0   3         s                     "apb smi            )   
            C      clock-controller@1f000000             mediatek,mt8192-mdpsys                                  f                     larb@1f002000             mediatek,mt8192-smi-larb                                              0   3         s                    "apb smi            )               8         chosen          serial0:921600n8          memory@40000000          memory               @                   	compatible interrupt-parent #address-cells #size-cells model ovl0 ovl-2l0 ovl-2l2 rdma0 rdma4 serial0 #clock-cells clocks clock-div clock-mult clock-output-names phandle clock-frequency device_type reg enable-method cpu-idle-states next-level-cache capacity-dmips-mhz cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges #power-domain-cells clock-names mediatek,infracfg assigned-clocks assigned-clock-parents regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #mbox-cells status #pwm-cells interrupts-extended interrupt-names phys wakeup-source mediatek,syscon-wakeup resets reset-names mediatek,apmixedsys mediatek,topckgen power-domains bus-range interrupt-map-mask interrupt-map #phy-cells mboxes mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus mediatek,rdma-fifo-size phy-names mediatek,larbs #iommu-cells mediatek,scp stdout-path 